litex: workshop: add some useful defines
These aren't used right now, but they'll come in handy for examples. Signed-off-by: Sean Cross <sean@xobs.io>
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@ -22,8 +22,10 @@ from lxsocsupport import up5kspram
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from valentyusb.usbcore import io as usbio
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from valentyusb.usbcore import io as usbio
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from valentyusb.usbcore.cpu import dummyusb
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from valentyusb.usbcore.cpu import dummyusb
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import argparse
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from migen import *
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from litex.soc.interconnect.csr import AutoCSR, CSRStatus, CSRStorage
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import argparse
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class BaseSoC(SoCCore):
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class BaseSoC(SoCCore):
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SoCCore.csr_map = {
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SoCCore.csr_map = {
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