Lots of style improvements.
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Tim 'mithro' Ansell
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1 changed files with 51 additions and 32 deletions
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README.md
83
README.md
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@ -1,3 +1,22 @@
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<style>
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.inner {
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max-width: 90%;
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}
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blockquote {
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border: 1px solid black;
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margin: 1em;
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padding: 1em;
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background: #ffdc8d;
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}
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blockquote:before {
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font-size: larger;
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font-weight: bolder;
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font-variant: small-caps;
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content: "Extra Information";
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}
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</style>
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# Fomu Workshop
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@ -10,7 +29,11 @@ FPGAs are complex, weird things, so we'll take a gentle approach and start out b
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## Required Software
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Fomu requires specialized software. This software is provided for Linux x86/64, macOS, and Windows, via [Fomu Toolchain](https://github.com/im-tomu/fomu-toolchain/releases/latest). If you're taking this workshop as a class, the toolchain are provided on the USB disk.
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Fomu requires specialized software. This software is provided for Linux x86/64, macOS, and Windows, via [Fomu Toolchain](https://github.com/im-tomu/fomu-toolchain/releases/latest).
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Debian packages are also [available for Raspberry Pi](https://github.com/im-tomu/fomu-raspbian-packages).
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If you're taking this workshop as a class, the toolchain are provided on the USB disk.
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To install the software, extract it somewhere on your computer, then open up a terminal window and add that directory to your PATH:
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@ -24,24 +47,18 @@ To confirm installation, run the `yosys` command and confirm you get the followi
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FIXME: Put output here!
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```
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<span class="extra">
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Debian packages are also [available for Raspberry Pi](https://github.com/im-tomu/fomu-raspbian-packages). For other platforms, please see the people running the workshop.
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The [Fomu Toolchain](https://github.com/im-tomu/fomu-toolchain/releases/latest) consists of the following tools;
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| Tool | Purpose |
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| ---- |------------------ |
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| **[yosys](https://github.com/YosysHQ/yosys)** | Verilog synthesis |
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| **[nextpnr-ice40](https://github.com/YosysHQ/nextpnr)** | FPGA place-and-route |
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| **[icestorm](https://github.com/cliffordwolf/icestorm)** | FPGA bitstream packing |
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| **[riscv toolchain](https://www.sifive.com/boards/)** | Compile code for a RISC-V softcore |
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| **[dfu-util](https://dfu-util.sourceforge.net/)** | Load a bitstream or code onto Fomu |
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| **[python](https://python.org/)** | Convert Migen/Litex code to Verilog |
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| **[wishbone-tool](https://github.com/xobs/wishbone-utils/)** | Interact with Fomu over USB |
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| **serial console** | Interact with Python over a virtual console |
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</span>
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> The [Fomu Toolchain](https://github.com/im-tomu/fomu-toolchain/releases/latest) consists of the following tools;
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>
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> | Tool | Purpose |
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> | ---- |------------------ |
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> | **[yosys](https://github.com/YosysHQ/yosys)** | Verilog synthesis |
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> | **[nextpnr-ice40](https://github.com/YosysHQ/nextpnr)** | FPGA place-and-route |
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> | **[icestorm](https://github.com/cliffordwolf/icestorm)** | FPGA bitstream packing |
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> | **[riscv toolchain](https://www.sifive.com/boards/)** | Compile code for a RISC-V softcore |
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> | **[dfu-util](https://dfu-util.sourceforge.net/)** | Load a bitstream or code onto Fomu |
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> | **[python](https://python.org/)** | Convert Migen/Litex code to Verilog |
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> | **[wishbone-tool](https://github.com/xobs/wishbone-utils/)** | Interact with Fomu over USB |
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> | **serial console** | Interact with Python over a virtual console |
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## Required Hardware
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@ -183,7 +200,7 @@ You can check with ```id $USER``` if your user really is in the plugdev group.
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Create a file named ```/etc/udev/rules.d/99-fomu.rules``` and add the
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following:
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```
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```udev
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SUBSYSTEM=="usb", ATTRS{idVendor}=="1209", ATTRS{idProduct}=="5bf0", MODE="0664", GROUP="plugdev"
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```
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@ -623,18 +640,18 @@ $
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You can load `blink.bin` onto Fomu by using the same `dfu-util -D` command we've been using. The LED should begin blinking on and off regularly, indicating your bitstream was successfully loaded.
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When writing HDL, a tool called `yosys` is used to convert the human readable verilog into a netlist representation, this is called synthesis. Once we have the netlist representation a tool called `nextpnr` performs an operation called "place and route" which makes it something that will actually run on the FPGA. This is all done for you using the `Makefile` in the `verilog-blink` directory.
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A big feature of `nextpnr` over its predecessor, is the fact that it is timing-driven. This means that a design will be generated with a given clock domain guaranteed to perform fast enough.
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When the `make` command runs `nextpnr-ice40` you will see the following included in the output;
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```
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Max frequency for clock 'clk12': 24.63 MHz (PASS at 12.00 MHz)
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Max frequency for clock 'clk48_1': 60.66 MHz (PASS at 48.00 MHz)
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Max frequency for clock 'clkraw': 228.05 MHz (PASS at 48.00 MHz)
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```
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This output example above shows we could run `clk12` at up to 24.63 MHz and it would still be stable, even though we only requested 12.00 MHz. Note that there is some variation between designs depending on how the placer and router decided to lay things out, so your exact frequency numbers might be different.
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> When writing HDL, a tool called `yosys` is used to convert the human readable verilog into a netlist representation, this is called synthesis. Once we have the netlist representation a tool called `nextpnr` performs an operation called "place and route" which makes it something that will actually run on the FPGA. This is all done for you using the `Makefile` in the `verilog-blink` directory.
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>
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> A big feature of `nextpnr` over its predecessor, is the fact that it is timing-driven. This means that a design will be generated with a given clock domain guaranteed to perform fast enough.
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>
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> When the `make` command runs `nextpnr-ice40` you will see the following included in the output;
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> ```
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> Max frequency for clock 'clk12': 24.63 MHz (PASS at 12.00 MHz)
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> Max frequency for clock 'clk48_1': 60.66 MHz (PASS at 48.00 MHz)
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> Max frequency for clock 'clkraw': 228.05 MHz (PASS at 48.00 MHz)
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> ```
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>
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> This output example above shows we could run `clk12` at up to 24.63 MHz and it would still be stable, even though we only requested 12.00 MHz. Note that there is some variation between designs depending on how the placer and router decided to lay things out, so your exact frequency numbers might be different.
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## Migen and LiteX
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@ -764,3 +781,5 @@ csr_register,rgb_output,0xe0006800,1,rw
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```
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We can use `wishbone-tool` to write values to `0xe0006800` and see them take effect immediately.
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