diff --git a/README.md b/README.md
index fcc8b3a..7f6f54a 100644
--- a/README.md
+++ b/README.md
@@ -607,7 +607,9 @@ There is an additional RISC-V demo in the workshop.  The `riscv-usb-cdcacm` dire
 
 The two most common **H**ardware **D**escription **Language** are Verilog and VHDL (the toolchain we are using only supports Verilog).
 
-### Verilog "Hello world!"
+### Verilog
+
+#### "Hello world!" - Blink an LED
 
 The canonical "Hello, world!" of hardware is to blink an LED.  The directory `verilog-blink` contains a Verilog example of a blink project.  This takes the 48 MHz clock and divides it down by a large number so you get an on/off pattern.  It also exposes some of the signals on the touchpads, making it possible to probe them with an oscilloscope.
 
@@ -667,7 +669,13 @@ You can load `blink.bin` onto Fomu by using the same `dfu-util -D` command we've
 
 ### Migen and LiteX
 
-Recall that Migen is an HDL embedded in Python, and LiteX provides us with a Wishbone abstraction layer.  There really is no reason we need to include a CPU with our design, but we can still reuse the USB Wishbone bridge in order to write HDL code.
+#### "Hello world!" - Blink an LED
+
+FIXME: Add the Migen and LiteX equivalent for the Verilog above.
+
+#### Wishbone Bus
+
+Migen is an HDL embedded in Python, and LiteX provides us with a Wishbone abstraction layer.  There really is no reason we need to include a CPU with our design, but we can still reuse the USB Wishbone bridge in order to write HDL code.
 
 We can use `DummyUsb` to respond to USB requests and bridge USB to Wishbone, and rely on LiteX to generate registers and wire them to hardware signals.  We can still use `wishbone-tool` to read and write memory, and with a wishbone bridge we can actually have code running on our local system that can read and write memory on Fomu.
 
@@ -734,6 +742,12 @@ Done!
 $
 ```
 
+If you get an error message about missing modules, check you have all submodules cloned and setup with;
+```sh
+$ git submodule update --recursive --init
+$
+```
+
 Take a look at `test/csr.csv`.  This describes the various regions present in our design.  You can see `memory_region,sram,0x10000000,131072`, which indicates the RAM is 128 kilobytes long and is located at `0x10000000`, just as when we had a CPU.  You can also see the timer, which is a feature that comes as part of LiteX.  Let's try reading and writing RAM:
 
 ```sh