pingu_98/fomu-workshop
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

README: Add a note about LUTs

Browse source 
Indicate that they're n-input, and note the difference between FPGA families.
This commit is contained in:
Sean Cross 2019-08-21 09:59:49 +02:00 committed by GitHub
parent 1ce00d2fcc
commit 8247c0de96
No known key found for this signature in database
GPG key ID: 4AEE18F83AFDEB23
1 changed files with 2 additions and 0 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
README.md
View file

@ -66,6 +66,8 @@ To do this, we turn to a truth table:
For example, to create a LUT that acted as an AND gate, we would define O to be 0 for everything except the last column. To create a NAND gate, we would define O to be 1 for everything from the last column. For example, to create a LUT that acted as an AND gate, we would define O to be 0 for everything except the last column. To create a NAND gate, we would define O to be 1 for everything from the last column.
FPGA LUTs are almost always _n_-inputs to 1-output. The ICE family of FPGAs from Lattice have 4-input LUTs. Xilinx parts tend to have 5- or 6-input LUTs which generally means they can do more logic in fewer LUTs. Comparing LUT count between FPGAs is a bit like comparing clock speed between different CPUs - not entirely accurate, but certainly a helpful rule of thumb.
It is from this simple primitive that we build up the building blocks of FPGA design. It is from this simple primitive that we build up the building blocks of FPGA design.
### Turning code into gates ### Turning code into gates