From b1c2b36cb16584bf9bac3fee567cfc1278c1bf33 Mon Sep 17 00:00:00 2001 From: Sean Cross Date: Wed, 19 Jun 2019 09:51:22 -0700 Subject: [PATCH] initial commit Signed-off-by: Sean Cross --- .gitattributes | 22 + .gitignore | 12 + .gitmodules | 24 + bin/litex_read_verilog | 14 + bin/litex_server | 14 + bin/litex_sim | 14 + bin/litex_simple | 14 + bin/litex_term | 14 + bin/mkmscimg | 14 + deps/litedram | 1 + deps/litescope | 1 + deps/litex | 1 + deps/litex_boards | 1 + deps/lxsocsupport | 1 + deps/migen | 1 + deps/pyserial | 1 + deps/valentyusb | 1 + lxbuildenv.py | 554 +++++++ rtl/2-stage-1024-cache.v | 3289 ++++++++++++++++++++++++++++++++++++++ rtl/spimemio.v | 579 +++++++ workshop.py | 330 ++++ 21 files changed, 4902 insertions(+) create mode 100644 .gitattributes create mode 100644 .gitignore create mode 100644 .gitmodules create mode 100755 bin/litex_read_verilog create mode 100755 bin/litex_server create mode 100755 bin/litex_sim create mode 100755 bin/litex_simple create mode 100755 bin/litex_term create mode 100755 bin/mkmscimg create mode 160000 deps/litedram create mode 160000 deps/litescope create mode 160000 deps/litex create mode 160000 deps/litex_boards create mode 160000 deps/lxsocsupport create mode 160000 deps/migen create mode 160000 deps/pyserial create mode 160000 deps/valentyusb create mode 100644 lxbuildenv.py create mode 100644 rtl/2-stage-1024-cache.v create mode 100644 rtl/spimemio.v create mode 100644 workshop.py diff --git a/.gitattributes b/.gitattributes new file mode 100644 index 0000000..978e064 --- /dev/null +++ b/.gitattributes @@ -0,0 +1,22 @@ +*.py text eol=lf +*.sh text eol=lf +LICENSE text eol=lf +README.* text eol=lf +*.interface text eol=lf +*.jig text eol=lf +*.logger text eol=lf +*.scenario text eol=lf +*.test text eol=lf +*.trigger text eol=lf +*.c text eol=lf +*.S text eol=lf +*.h text eol=lf +*.ld text eol=lf +hw/bin/* text eol=lf +Makefile text eol=lf +*.service text eol=lf +*.png binary +*.jpg binary +*.bin binary +*.elf binary +*.bin binary diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..5c82b8f --- /dev/null +++ b/.gitignore @@ -0,0 +1,12 @@ +.obj/ +*.swp +*.swo +*~ +*.bin +*.dfu +*.ihex +*.elf +.vscode/ +build/ +__pycache__/ +.env diff --git a/.gitmodules b/.gitmodules new file mode 100644 index 0000000..a142058 --- /dev/null +++ b/.gitmodules @@ -0,0 +1,24 @@ +[submodule "deps/migen"] + path = deps/migen + url = https://github.com/m-labs/migen.git +[submodule "deps/litex"] + path = deps/litex + url = https://github.com/enjoy-digital/litex.git +[submodule "deps/litex_boards"] + path = deps/litex_boards + url = https://github.com/litex-hub/litex-boards.git +[submodule "deps/litescope"] + path = deps/litescope + url = https://github.com/enjoy-digital/litescope.git +[submodule "deps/pyserial"] + path = deps/pyserial + url = https://github.com/pyserial/pyserial.git +[submodule "deps/lxsocsupport"] + path = deps/lxsocsupport + url = https://github.com/xobs/lxsocsupport.git +[submodule "deps/valentyusb"] + path = deps/valentyusb + url = https://github.com/im-tomu/valentyusb.git +[submodule "deps/litedram"] + path = deps/litedram + url = https://github.com/enjoy-digital/litedram.git diff --git a/bin/litex_read_verilog b/bin/litex_read_verilog new file mode 100755 index 0000000..fb8d178 --- /dev/null +++ b/bin/litex_read_verilog @@ -0,0 +1,14 @@ +#!/usr/bin/env python3 + +import sys +import os + +# This script lives in the "bin" directory, but uses a helper script in the parent +# directory. Obtain the current path so we can get the absolute parent path. +script_path = os.path.dirname(os.path.realpath( + __file__)) + os.path.sep + os.path.pardir + os.path.sep +sys.path.insert(0, script_path) +import lxbuildenv + +from litex.tools.litex_read_verilog import main +main() diff --git a/bin/litex_server b/bin/litex_server new file mode 100755 index 0000000..9523fb5 --- /dev/null +++ b/bin/litex_server @@ -0,0 +1,14 @@ +#!/usr/bin/env python3 + +import sys +import os + +# This script lives in the "bin" directory, but uses a helper script in the parent +# directory. Obtain the current path so we can get the absolute parent path. +script_path = os.path.dirname(os.path.realpath( + __file__)) + os.path.sep + os.path.pardir + os.path.sep +sys.path.insert(0, script_path) +import lxbuildenv + +from litex.tools.litex_server import main +main() diff --git a/bin/litex_sim b/bin/litex_sim new file mode 100755 index 0000000..4964d63 --- /dev/null +++ b/bin/litex_sim @@ -0,0 +1,14 @@ +#!/usr/bin/env python3 + +import sys +import os + +# This script lives in the "bin" directory, but uses a helper script in the parent +# directory. Obtain the current path so we can get the absolute parent path. +script_path = os.path.dirname(os.path.realpath( + __file__)) + os.path.sep + os.path.pardir + os.path.sep +sys.path.insert(0, script_path) +import lxbuildenv + +from litex.tools.litex_sim import main +main() diff --git a/bin/litex_simple b/bin/litex_simple new file mode 100755 index 0000000..eea9a6a --- /dev/null +++ b/bin/litex_simple @@ -0,0 +1,14 @@ +#!/usr/bin/env python3 + +import sys +import os + +# This script lives in the "bin" directory, but uses a helper script in the parent +# directory. Obtain the current path so we can get the absolute parent path. +script_path = os.path.dirname(os.path.realpath( + __file__)) + os.path.sep + os.path.pardir + os.path.sep +sys.path.insert(0, script_path) +import lxbuildenv + +from litex.boards.targets.simple import main +main() diff --git a/bin/litex_term b/bin/litex_term new file mode 100755 index 0000000..0e2590c --- /dev/null +++ b/bin/litex_term @@ -0,0 +1,14 @@ +#!/usr/bin/env python3 + +import sys +import os + +# This script lives in the "bin" directory, but uses a helper script in the parent +# directory. Obtain the current path so we can get the absolute parent path. +script_path = os.path.dirname(os.path.realpath( + __file__)) + os.path.sep + os.path.pardir + os.path.sep +sys.path.insert(0, script_path) +import lxbuildenv + +from litex.tools.litex_term import main +main() diff --git a/bin/mkmscimg b/bin/mkmscimg new file mode 100755 index 0000000..456673c --- /dev/null +++ b/bin/mkmscimg @@ -0,0 +1,14 @@ +#!/usr/bin/env python3 + +import sys +import os + +# This script lives in the "bin" directory, but uses a helper script in the parent +# directory. Obtain the current path so we can get the absolute parent path. +script_path = os.path.dirname(os.path.realpath( + __file__)) + os.path.sep + os.path.pardir + os.path.sep +sys.path.insert(0, script_path) +import lxbuildenv + +from litex.soc.software.mkmscimg import main +main() diff --git a/deps/litedram b/deps/litedram new file mode 160000 index 0000000..690e4f8 --- /dev/null +++ b/deps/litedram @@ -0,0 +1 @@ +Subproject commit 690e4f848ffccebb437a19b498a2adb840ce1e08 diff --git a/deps/litescope b/deps/litescope new file mode 160000 index 0000000..2474ce9 --- /dev/null +++ b/deps/litescope @@ -0,0 +1 @@ +Subproject commit 2474ce9db23e4d06bff4bbeacf0051efa3042f37 diff --git a/deps/litex b/deps/litex new file mode 160000 index 0000000..408d3f1 --- /dev/null +++ b/deps/litex @@ -0,0 +1 @@ +Subproject commit 408d3f1f7c5a4657dd9e964da4ed76f35cfd9e8f diff --git a/deps/litex_boards b/deps/litex_boards new file mode 160000 index 0000000..482a00a --- /dev/null +++ b/deps/litex_boards @@ -0,0 +1 @@ +Subproject commit 482a00aa768159fe23622a08e67a503f39007967 diff --git a/deps/lxsocsupport b/deps/lxsocsupport new file mode 160000 index 0000000..74f1333 --- /dev/null +++ b/deps/lxsocsupport @@ -0,0 +1 @@ +Subproject commit 74f133340144630e000f91e466ac5107f87a8d5a diff --git a/deps/migen b/deps/migen new file mode 160000 index 0000000..562c046 --- /dev/null +++ b/deps/migen @@ -0,0 +1 @@ +Subproject commit 562c0466443f859d6cf0c87a0bb50db094d27cf4 diff --git a/deps/pyserial b/deps/pyserial new file mode 160000 index 0000000..acab9d2 --- /dev/null +++ b/deps/pyserial @@ -0,0 +1 @@ +Subproject commit acab9d2c0efb63323faebfd5e3405d77cd4b5617 diff --git a/deps/valentyusb b/deps/valentyusb new file mode 160000 index 0000000..3052a16 --- /dev/null +++ b/deps/valentyusb @@ -0,0 +1 @@ +Subproject commit 3052a16d9f18360f407ce7a4d0cbd82e24cb4768 diff --git a/lxbuildenv.py b/lxbuildenv.py new file mode 100644 index 0000000..df0f555 --- /dev/null +++ b/lxbuildenv.py @@ -0,0 +1,554 @@ +#!/usr/bin/env python3 + +# This script enables easy, cross-platform building without the need +# to install third-party Python modules. + +import sys +import os +import subprocess +import argparse + + +DEPS_DIR = "deps" + +DEFAULT_DEPS = { + 'migen': 'https://github.com/m-labs/migen.git', + 'litex': 'https://github.com/enjoy-digital/litex.git', + 'litedram': 'https://github.com/enjoy-digital/litedram.git', + 'litex_boards': 'https://github.com/litex-hub/litex-boards.git', + 'litescope': 'https://github.com/enjoy-digital/litescope.git', + 'pyserial': 'https://github.com/pyserial/pyserial.git', +} + +OPTIONAL_DEPS = { + 'liteeth': 'https://github.com/enjoy-digital/liteeth.git', + 'liteusb': 'https://github.com/enjoy-digital/liteusb.git', + 'litepcie': 'https://github.com/enjoy-digital/litepcie.git', + 'litesdcard': 'https://github.com/enjoy-digital/litesdcard.git', + 'liteiclink': 'https://github.com/enjoy-digital/liteiclink.git', + 'litevideo': 'https://github.com/enjoy-digital/litevideo.git', + 'usb': 'https://github.com/pyusb/pyusb.git', +} + +# Obtain the path to this script, plus a trailing separator. This will +# be used later on to construct various environment variables for paths +# to a variety of support directories. +script_path = os.path.dirname(os.path.realpath(__file__)) + os.path.sep + +# Look through the specified file for known variables to get the dependency list +def get_required_dependencies(filename): + import ast + + # Always check the Python version + dependencies = { + 'python': 1 + } + main_src = "" + + try: + with open(sys.argv[0], 'r') as f: + main_src = f.read() + main_ast = ast.parse(main_src, filename=filename) + except: + return list(dependencies.keys()) + + # Iterate through the top-level nodes looking for variables named + # LX_DEPENDENCIES or LX_DEPENDENCY and get the values that are + # assigned to them. + for node in ast.iter_child_nodes(main_ast): + if isinstance(node, ast.Assign): + value = node.value + for target in node.targets: + if isinstance(target, ast.Name): + if target.id == "LX_DEPENDENCIES" or target.id == "LX_DEPENDENCY": + if isinstance(value, (ast.List, ast.Tuple)): + for elt in value.elts: + if isinstance(elt, ast.Str): + dependencies[elt.s] = 1 + elif isinstance(value, ast.Str): + dependencies[value.s] = 1 + + # Set up sub-dependencies + if 'riscv' in dependencies: + dependencies['make'] = 1 + return list(dependencies.keys()) + +def get_python_path(script_path, args): + # Python has no concept of a local dependency path, such as the C `-I`` + # switch, or the nodejs `node_modules` path, or the rust cargo registry. + # Instead, it relies on an environment variable to append to the search + # path. + # Construct this variable by adding each subdirectory under the `deps/` + # directory to the PYTHONPATH environment variable. + python_path = [] + if os.path.isdir(script_path + DEPS_DIR): + for dep in os.listdir(script_path + DEPS_DIR): + dep = script_path + DEPS_DIR + os.path.sep + dep + if os.path.isdir(dep): + python_path.append(dep) + return python_path + +def fixup_env(script_path, args): + os.environ["PYTHONPATH"] = os.pathsep.join(get_python_path(script_path, 0)) + + # Set the "LXBUILDENV_REEXEC" variable to prevent the script from continuously + # reinvoking itself. + os.environ["LXBUILDENV_REEXEC"] = "1" + + # Python randomizes the order in which it traverses hashes, and Migen uses + # hashes an awful lot when bringing together modules. As such, the order + # in which Migen generates its output Verilog will change with every run, + # and the addresses for various modules will change. + # Make builds deterministic so that the generated Verilog code won't change + # across runs. + os.environ["PYTHONHASHSEED"] = "1" + + # Some Makefiles are invoked as part of the build process, and those Makefiles + # occasionally have calls to Python. Ensure those Makefiles use the same + # interpreter that this script is using. + os.environ["PYTHON"] = sys.executable + + # Set the environment variable "V" to 1. This causes Makefiles to print + # the commands they run, which makes them easier to debug. + if "lx_verbose" in args and args.lx_verbose: + os.environ["V"] = "1" + + # If the user just wanted to print the environment variables, do that and quit. + if args.lx_print_env: + print("PYTHONPATH={}".format(os.environ["PYTHONPATH"])) + print("PYTHONHASHSEED={}".format(os.environ["PYTHONHASHSEED"])) + print("PYTHON={}".format(sys.executable)) + print("LXBUILDENV_REEXEC={}".format(os.environ["LXBUILDENV_REEXEC"])) + + sys.exit(0) + +# Equivalent to the powershell Get-Command, and kinda like `which` +def get_command(cmd): + if os.name == 'nt': + path_ext = os.environ["PATHEXT"].split(os.pathsep) + else: + path_ext = [""] + for ext in path_ext: + for path in os.environ["PATH"].split(os.pathsep): + + if os.path.exists(path + os.path.sep + cmd + ext): + return path + os.path.sep + cmd + ext + return None + +def check_python_version(args): + import platform + # Litex / Migen require Python 3.5 or newer. Ensure we're running + # under a compatible version of Python. + if sys.version_info[:3] < (3, 5): + return (False, + "python: You need Python 3.5+ (version {} found)".format(sys.version_info[:3])) + return (True, "python 3.5+: ok (Python {} found)".format(platform.python_version())) + +def check_vivado(args): + vivado_path = get_command("vivado") + if vivado_path == None: + # Look for the default Vivado install directory + if os.name == 'nt': + base_dir = r"C:\Xilinx\Vivado" + else: + base_dir = "/opt/Xilinx/Vivado" + if os.path.exists(base_dir): + for file in os.listdir(base_dir): + bin_dir = base_dir + os.path.sep + file + os.path.sep + "bin" + if os.path.exists(bin_dir + os.path.sep + "vivado"): + os.environ["PATH"] += os.pathsep + bin_dir + vivado_path = bin_dir + break + if vivado_path == None: + return (False, "toolchain not found in your PATH", "download it from https://www.xilinx.com/support/download.html") + return (True, "found at {}".format(vivado_path)) + +def check_cmd(args, cmd, name=None, fix=None): + if name is None: + name = cmd + path = get_command(cmd) + if path == None: + return (False, name + " not found in your PATH", fix) + return (True, "found at {}".format(path)) + +def check_make(args): + return check_cmd(args, "make", "GNU Make") + +def check_riscv(args): + riscv64 = check_cmd(args, "riscv64-unknown-elf-gcc", "riscv toolchain", "download it from https://www.sifive.com/boards/") + if riscv64[0] == True: + return riscv64 + + riscv32 = check_cmd(args, "riscv32-unknown-elf-gcc", "riscv toolchain", "download it from https://www.sifive.com/boards/") + if riscv32[0] == True: + return riscv32 + + return riscv64 + +def check_yosys(args): + return check_cmd(args, "yosys") + +def check_arachne(args): + return check_cmd(args, "arachne-pnr") + +def check_icestorm(args): + return check_cmd(args, "icepack") and check_cmd(args, "nextpnr-ice40") + +dependency_checkers = { + 'python': check_python_version, + 'vivado': check_vivado, + 'make': check_make, + 'riscv': check_riscv, + 'yosys': check_yosys, + 'arachne-pnr': check_arachne, + 'icestorm': check_icestorm, +} + +# Validate that the required dependencies (Vivado, compilers, etc.) +# have been installed. +def check_dependencies(args, dependency_list): + + dependency_errors = 0 + for dependency_name in dependency_list: + if not dependency_name in dependency_checkers: + print('WARNING: Unrecognized dependency "{}"'.format(dependency_name)) + continue + result = dependency_checkers[dependency_name](args) + if result[0] == False: + if len(result) > 2: + print('{}: {} -- {}'.format(dependency_name, result[1], result[2])) + else: + print('{}: {}'.format(dependency_name, result[1])) + dependency_errors = dependency_errors + 1 + + elif args.lx_check_deps or args.lx_verbose: + print('dependency: {}: {}'.format(dependency_name, result[1])) + if dependency_errors > 0: + if args.lx_ignore_deps: + print('{} missing dependencies were found but continuing anyway'.format(dependency_errors)) + else: + raise SystemExit(str(dependency_errors) + + " missing dependencies were found") + + if args.lx_check_deps: + sys.exit(0) + +# Return True if the given tree needs to be initialized +def check_module_recursive(root_path, depth, verbose=False, breadcrumbs=[]): + if verbose: + print('git-dep: checking if "{}" requires updating (depth: {})...'.format(root_path, depth)) + + # If the directory isn't a valid git repo, initialization is required + git_dir_cmd = subprocess.Popen(["git", "rev-parse", "--show-toplevel"], + cwd=root_path, + stdout=subprocess.PIPE, + stderr=subprocess.PIPE) + (git_stdout, _) = git_dir_cmd.communicate() + if git_dir_cmd.wait() != 0: + if verbose: + print('git-dep: missing git directory, starting update...') + return True + git_dir = git_stdout.decode().strip() + + if git_dir in breadcrumbs: + if verbose: + print('git-dep: root path {} is not in git path'.format(root_path)) + return True + breadcrumbs.append(git_dir) + + if not os.path.exists(git_dir + os.path.sep + '.git'): + if verbose: + print('git-dep: .git not found in "{}"'.format(git_dir)) + return True + + # If there are no submodules, no initialization needs to be done + if not os.path.isfile(git_dir + os.path.sep + '.gitmodules'): + if verbose: + print('git-dep: .gitmodules not found in "{}", so not updating'.format(git_dir)) + return False + + # Loop through the gitmodules to check all submodules + gitmodules = open(git_dir + os.path.sep + '.gitmodules', 'r') + for line in gitmodules: + parts = line.split("=", 2) + if parts[0].strip() == "path": + path = parts[1].strip() + if check_module_recursive(git_dir + os.path.sep + path, depth + 1, verbose=verbose, breadcrumbs=breadcrumbs): + return True + return False + +# Determine whether we need to invoke "git submodules init --recurse" +def check_submodules(script_path, args): + if check_module_recursive(script_path, 0, verbose=args.lx_verbose): + print("Missing submodules -- updating") + subprocess.Popen(["git", "submodule", "update", + "--init", "--recursive"], cwd=script_path).wait() + elif args.lx_verbose: + print("Submodule check: Submodules found") + + +def lx_git(cmd, *args): + import subprocess + git_cmd = ["git", cmd] + if args is not None: + for arg in args: + git_cmd = git_cmd + [arg] + subprocess.call(git_cmd) + +def lx_print_deps(): + print('Known dependencies:') + for dep in dependency_checkers.keys(): + print(' {}'.format(dep)) + print('To define a dependency, add a variable inside {} at the top level called LX_DEPENDENCIES and assign it a list or tuple.'.format(sys.argv[0])) + print('For example:') + print('LX_DEPENDENCIES = ("riscv", "vivado")') + + +def lx_main(args): + if args.lx_print_env: + fixup_env(script_path, args) + + elif args.lx_print_deps: + lx_print_deps() + + elif args.lx_run is not None: + script_name=args.lx_run[0] + get_required_dependencies(script_name) + + fixup_env(script_path, args) + check_submodules(script_path, args) + + try: + sys.exit(subprocess.Popen( + [sys.executable] + [script_name] + args.lx_run[1:]).wait()) + except: + sys.exit(1) + elif args.init: + if args.main is None: + main_name = os.getcwd().split(os.path.sep)[-1] + '.py' + new_main_name = input('What would you like your main program to be called? [' + main_name + '] ') + if new_main_name is not None and new_main_name != "": + main_name = new_main_name + else: + main_name = args.main + if not main_name.endswith('.py'): + main_name = main_name + '.py' + + if args.no_git: + print("skipping git initialization") + else: + if not os.path.exists(DEPS_DIR): + os.mkdir(DEPS_DIR) + + if not os.path.exists(".git"): + print("initializing git repository") + lx_git('init') + else: + print("using existing git repository") + lx_git('add', str(__file__)) + + for dep_name, dep_url in DEFAULT_DEPS.items(): + dest_path = '{}{}{}'.format(DEPS_DIR, '/', dep_name) + if not os.path.exists(dest_path): + lx_git('submodule', 'add', dep_url, dest_path) + lx_git('add', dest_path) + + lx_git('submodule', 'update', '--init', '--recursive') + + if args.no_bin: + print("skipping bin/ initialization") + elif os.path.exists("bin"): + print("bin/ directory exists -- remove bin/ directory to re-initialize") + else: + bin_tools = { + 'mkmscimg': 'litex.soc.software.mkmscimg', + 'litex_term': 'litex.tools.litex_term', + 'litex_server': 'litex.tools.litex_server', + 'litex_sim': 'litex.tools.litex_sim', + 'litex_read_verilog': 'litex.tools.litex_read_verilog', + 'litex_simple': 'litex.boards.targets.simple', + } + bin_template = """#!/usr/bin/env python3 + +import sys +import os + +# This script lives in the "bin" directory, but uses a helper script in the parent +# directory. Obtain the current path so we can get the absolute parent path. +script_path = os.path.dirname(os.path.realpath( + __file__)) + os.path.sep + os.path.pardir + os.path.sep +sys.path.insert(0, script_path) +import lxbuildenv + +""" + print("Creating binaries") + os.mkdir("bin") + for bin_name, python_module in bin_tools.items(): + with open('bin' + os.path.sep + bin_name, 'w', newline='\n') as new_bin: + new_bin.write(bin_template) + new_bin.write('from ' + python_module + ' import main\n') + new_bin.write('main()\n') + import stat + os.chmod('bin' + os.path.sep + bin_name, stat.S_IRUSR | stat.S_IRGRP | stat.S_IROTH | stat.S_IXUSR | stat.S_IXGRP | stat.S_IXOTH) + if not args.no_git: + lx_git('add', '--chmod=+x', 'bin' + os.path.sep + bin_name) + + if os.path.exists(main_name): + print("skipping creation of {}: file exists".format(main_name)) + else: + print("creating main program {}".format(main_name)) + with open(main_name, 'w') as m: + program_template = """#!/usr/bin/env python3 +# This variable defines all the external programs that this module +# relies on. lxbuildenv reads this variable in order to ensure +# the build will finish without exiting due to missing third-party +# programs. +LX_DEPENDENCIES = ["riscv", "vivado"] + +# Import lxbuildenv to integrate the deps/ directory +import lxbuildenv + +# Disable pylint's E1101, which breaks completely on migen +#pylint:disable=E1101 + +from migen import * +from litex.build.xilinx import VivadoProgrammer, XilinxPlatform +from litex.build.generic_platform import Pins, IOStandard +from litex.soc.integration import SoCSDRAM +from litex.soc.integration.builder import Builder +from litex.soc.integration.soc_core import csr_map_update + +_io = [ + ("clk50", 0, Pins("J19"), IOStandard("LVCMOS33")), +] + +class Platform(XilinxPlatform): + def __init__(self, toolchain="vivado", programmer="vivado", part="35"): + part = "xc7a" + part + "t-fgg484-2" + def create_programmer(self): + if self.programmer == "vivado": + return VivadoProgrammer(flash_part="n25q128-3.3v-spi-x1_x2_x4") + else: + raise ValueError("{} programmer is not supported" + .format(self.programmer)) + + def do_finalize(self, fragment): + XilinxPlatform.do_finalize(self, fragment) + +class BaseSoC(SoCSDRAM): + csr_peripherals = [ + "ddrphy", +# "dna", + "xadc", + "cpu_or_bridge", + ] + csr_map_update(SoCSDRAM.csr_map, csr_peripherals) + + def __init__(self, platform, **kwargs): + clk_freq = int(100e6) + +def main(): + platform = Platform() + soc = BaseSoC(platform) + builder = Builder(soc, output_dir="build", csr_csv="test/csr.csv") + vns = builder.build() + soc.do_exit(vns) + +if __name__ == "__main__": + main() +""" + m.write(program_template) + if not args.no_git: + lx_git("add", main_name) + else: + return False + return True + +# For the main command, parse args and hand it off to main() +if __name__ == "__main__": + parser = argparse.ArgumentParser( + description="Wrap Python code to enable quickstart", + add_help=False) + parser.add_argument( + "-h", "--help", '--lx-help', help="show this help message and exit", action="help" + ) + parser.add_argument( + '-i', '--init', '--lx-init', help='initialize a new project', action="store_true" + ) + parser.add_argument( + '-m', '--main', '--lx-main', help='name of main project' + ) + parser.add_argument( + '--no-bin', '--lx-no-bin', help="don't create a bin/ directory" + ) + parser.add_argument( + '--no-git', '--lx-no-git', help="Don't create a git repository" + ) + parser.add_argument( + '-e', '--print-env', '--lx-print-env', dest="lx_print_env", help="print environment variable listing for pycharm, vscode, or bash", action="store_true" + ) + parser.add_argument( + '-d', '--print-deps', '--lx-print-deps', dest="lx_print_deps", help="print all possible dependencies and then exit", action="store_true" + ) + parser.add_argument( + "--lx-verbose", help="increase verboseness of some processes", action="store_true" + ) + parser.add_argument( + '-r', '--run', '--lx-run', dest='lx_run', help="run the given script under lxbuildenv", nargs=argparse.REMAINDER + ) + args = parser.parse_args() + + if not lx_main(args): + parser.print_help() + +elif not os.path.isfile(sys.argv[0]): + print("lxbuildenv doesn't operate while in interactive mode") + +elif "LXBUILDENV_REEXEC" not in os.environ: + parser = argparse.ArgumentParser( + description="Wrap Python code to enable quickstart", + add_help=False) + parser.add_argument( + "--lx-verbose", help="increase verboseness of some processes", action="store_true" + ) + parser.add_argument( + "--lx-print-env", help="print environment variable listing for pycharm, vscode, or bash", action="store_true" + ) + parser.add_argument( + "--lx-check-deps", help="check build environment for dependencies such as compiler and fpga tools and then exit", action="store_true" + ) + parser.add_argument( + "--lx-print-deps", help="print all possible dependencies and then exit", action="store_true" + ) + parser.add_argument( + "--lx-help", action="help" + ) + parser.add_argument( + "--lx-ignore-deps", help="try building even if dependencies are missing", action="store_true" + ) + (args, rest) = parser.parse_known_args() + + if args.lx_print_deps: + lx_print_deps() + sys.exit(0) + + deps = get_required_dependencies(sys.argv[0]) + + fixup_env(script_path, args) + check_dependencies(args, deps) + check_submodules(script_path, args) + + try: + sys.exit(subprocess.Popen( + [sys.executable] + [sys.argv[0]] + rest).wait()) + except: + sys.exit(1) +else: + # Overwrite the deps directory. + # Because we're running with a predefined PYTHONPATH, you'd think that + # the DEPS_DIR would be first. + # Unfortunately, setuptools causes the sitewide packages to take precedence + # over the PYTHONPATH variable. + # Work around this bug by inserting paths into the first index. + for path in get_python_path(script_path, None): + sys.path.insert(0, path) diff --git a/rtl/2-stage-1024-cache.v b/rtl/2-stage-1024-cache.v new file mode 100644 index 0000000..669e3a6 --- /dev/null +++ b/rtl/2-stage-1024-cache.v @@ -0,0 +1,3289 @@ +// Generator : SpinalHDL v1.3.3 git head : 8b8cd335eecbea3b5f1f970f218a982dbdb12d99 +// Date : 25/04/2019, 15:31:44 +// Component : VexRiscv + + +`define EnvCtrlEnum_defaultEncoding_type [1:0] +`define EnvCtrlEnum_defaultEncoding_NONE 2'b00 +`define EnvCtrlEnum_defaultEncoding_XRET 2'b01 +`define EnvCtrlEnum_defaultEncoding_ECALL 2'b10 +`define EnvCtrlEnum_defaultEncoding_EBREAK 2'b11 + +`define Src2CtrlEnum_defaultEncoding_type [1:0] +`define Src2CtrlEnum_defaultEncoding_RS 2'b00 +`define Src2CtrlEnum_defaultEncoding_IMI 2'b01 +`define Src2CtrlEnum_defaultEncoding_IMS 2'b10 +`define Src2CtrlEnum_defaultEncoding_PC 2'b11 + +`define Src1CtrlEnum_defaultEncoding_type [1:0] +`define Src1CtrlEnum_defaultEncoding_RS 2'b00 +`define Src1CtrlEnum_defaultEncoding_IMU 2'b01 +`define Src1CtrlEnum_defaultEncoding_PC_INCREMENT 2'b10 +`define Src1CtrlEnum_defaultEncoding_URS1 2'b11 + +`define AluCtrlEnum_defaultEncoding_type [1:0] +`define AluCtrlEnum_defaultEncoding_ADD_SUB 2'b00 +`define AluCtrlEnum_defaultEncoding_SLT_SLTU 2'b01 +`define AluCtrlEnum_defaultEncoding_BITWISE 2'b10 + +`define BranchCtrlEnum_defaultEncoding_type [1:0] +`define BranchCtrlEnum_defaultEncoding_INC 2'b00 +`define BranchCtrlEnum_defaultEncoding_B 2'b01 +`define BranchCtrlEnum_defaultEncoding_JAL 2'b10 +`define BranchCtrlEnum_defaultEncoding_JALR 2'b11 + +`define ShiftCtrlEnum_defaultEncoding_type [1:0] +`define ShiftCtrlEnum_defaultEncoding_DISABLE_1 2'b00 +`define ShiftCtrlEnum_defaultEncoding_SLL_1 2'b01 +`define ShiftCtrlEnum_defaultEncoding_SRL_1 2'b10 +`define ShiftCtrlEnum_defaultEncoding_SRA_1 2'b11 + +`define AluBitwiseCtrlEnum_defaultEncoding_type [1:0] +`define AluBitwiseCtrlEnum_defaultEncoding_XOR_1 2'b00 +`define AluBitwiseCtrlEnum_defaultEncoding_OR_1 2'b01 +`define AluBitwiseCtrlEnum_defaultEncoding_AND_1 2'b10 + +module InstructionCache ( + input io_flush, + input io_cpu_prefetch_isValid, + output reg io_cpu_prefetch_haltIt, + input [31:0] io_cpu_prefetch_pc, + input io_cpu_fetch_isValid, + input io_cpu_fetch_isStuck, + input io_cpu_fetch_isRemoved, + input [31:0] io_cpu_fetch_pc, + output [31:0] io_cpu_fetch_data, + input io_cpu_fetch_dataBypassValid, + input [31:0] io_cpu_fetch_dataBypass, + output io_cpu_fetch_mmuBus_cmd_isValid, + output [31:0] io_cpu_fetch_mmuBus_cmd_virtualAddress, + output io_cpu_fetch_mmuBus_cmd_bypassTranslation, + input [31:0] io_cpu_fetch_mmuBus_rsp_physicalAddress, + input io_cpu_fetch_mmuBus_rsp_isIoAccess, + input io_cpu_fetch_mmuBus_rsp_allowRead, + input io_cpu_fetch_mmuBus_rsp_allowWrite, + input io_cpu_fetch_mmuBus_rsp_allowExecute, + input io_cpu_fetch_mmuBus_rsp_exception, + input io_cpu_fetch_mmuBus_rsp_refilling, + output io_cpu_fetch_mmuBus_end, + input io_cpu_fetch_mmuBus_busy, + output [31:0] io_cpu_fetch_physicalAddress, + output io_cpu_fetch_cacheMiss, + output io_cpu_fetch_error, + output io_cpu_fetch_mmuRefilling, + output io_cpu_fetch_mmuException, + input io_cpu_fetch_isUser, + output io_cpu_fetch_haltIt, + input io_cpu_decode_isValid, + input io_cpu_decode_isStuck, + input [31:0] io_cpu_decode_pc, + output [31:0] io_cpu_decode_physicalAddress, + output [31:0] io_cpu_decode_data, + input io_cpu_fill_valid, + input [31:0] io_cpu_fill_payload, + output io_mem_cmd_valid, + input io_mem_cmd_ready, + output [31:0] io_mem_cmd_payload_address, + output [2:0] io_mem_cmd_payload_size, + input io_mem_rsp_valid, + input [31:0] io_mem_rsp_payload_data, + input io_mem_rsp_payload_error, + input clk, + input reset); + reg [23:0] _zz_10_; + reg [31:0] _zz_11_; + wire _zz_12_; + wire _zz_13_; + wire [0:0] _zz_14_; + wire [0:0] _zz_15_; + wire [23:0] _zz_16_; + reg _zz_1_; + reg _zz_2_; + reg lineLoader_fire; + reg lineLoader_valid; + reg [31:0] lineLoader_address; + reg lineLoader_hadError; + reg lineLoader_flushPending; + reg [5:0] lineLoader_flushCounter; + reg _zz_3_; + reg lineLoader_cmdSent; + reg lineLoader_wayToAllocate_willIncrement; + wire lineLoader_wayToAllocate_willClear; + wire lineLoader_wayToAllocate_willOverflowIfInc; + wire lineLoader_wayToAllocate_willOverflow; + reg [2:0] lineLoader_wordIndex; + wire lineLoader_write_tag_0_valid; + wire [4:0] lineLoader_write_tag_0_payload_address; + wire lineLoader_write_tag_0_payload_data_valid; + wire lineLoader_write_tag_0_payload_data_error; + wire [21:0] lineLoader_write_tag_0_payload_data_address; + wire lineLoader_write_data_0_valid; + wire [7:0] lineLoader_write_data_0_payload_address; + wire [31:0] lineLoader_write_data_0_payload_data; + wire _zz_4_; + wire [4:0] _zz_5_; + wire _zz_6_; + wire fetchStage_read_waysValues_0_tag_valid; + wire fetchStage_read_waysValues_0_tag_error; + wire [21:0] fetchStage_read_waysValues_0_tag_address; + wire [23:0] _zz_7_; + wire [7:0] _zz_8_; + wire _zz_9_; + wire [31:0] fetchStage_read_waysValues_0_data; + wire fetchStage_hit_hits_0; + wire fetchStage_hit_valid; + wire fetchStage_hit_error; + wire [31:0] fetchStage_hit_data; + wire [31:0] fetchStage_hit_word; + reg [23:0] ways_0_tags [0:31]; + reg [31:0] ways_0_datas [0:255]; + assign _zz_12_ = (! lineLoader_flushCounter[5]); + assign _zz_13_ = (lineLoader_flushPending && (! (lineLoader_valid || io_cpu_fetch_isValid))); + assign _zz_14_ = _zz_7_[0 : 0]; + assign _zz_15_ = _zz_7_[1 : 1]; + assign _zz_16_ = {lineLoader_write_tag_0_payload_data_address,{lineLoader_write_tag_0_payload_data_error,lineLoader_write_tag_0_payload_data_valid}}; + always @ (posedge clk) begin + if(_zz_2_) begin + ways_0_tags[lineLoader_write_tag_0_payload_address] <= _zz_16_; + end + end + + always @ (posedge clk) begin + if(_zz_6_) begin + _zz_10_ <= ways_0_tags[_zz_5_]; + end + end + + always @ (posedge clk) begin + if(_zz_1_) begin + ways_0_datas[lineLoader_write_data_0_payload_address] <= lineLoader_write_data_0_payload_data; + end + end + + always @ (posedge clk) begin + if(_zz_9_) begin + _zz_11_ <= ways_0_datas[_zz_8_]; + end + end + + always @ (*) begin + _zz_1_ = 1'b0; + if(lineLoader_write_data_0_valid)begin + _zz_1_ = 1'b1; + end + end + + always @ (*) begin + _zz_2_ = 1'b0; + if(lineLoader_write_tag_0_valid)begin + _zz_2_ = 1'b1; + end + end + + assign io_cpu_fetch_haltIt = io_cpu_fetch_mmuBus_busy; + always @ (*) begin + lineLoader_fire = 1'b0; + if(io_mem_rsp_valid)begin + if((lineLoader_wordIndex == (3'b111)))begin + lineLoader_fire = 1'b1; + end + end + end + + always @ (*) begin + io_cpu_prefetch_haltIt = (lineLoader_valid || lineLoader_flushPending); + if(_zz_12_)begin + io_cpu_prefetch_haltIt = 1'b1; + end + if((! _zz_3_))begin + io_cpu_prefetch_haltIt = 1'b1; + end + if(io_flush)begin + io_cpu_prefetch_haltIt = 1'b1; + end + end + + assign io_mem_cmd_valid = (lineLoader_valid && (! lineLoader_cmdSent)); + assign io_mem_cmd_payload_address = {lineLoader_address[31 : 5],(5'b00000)}; + assign io_mem_cmd_payload_size = (3'b101); + always @ (*) begin + lineLoader_wayToAllocate_willIncrement = 1'b0; + if(lineLoader_fire)begin + lineLoader_wayToAllocate_willIncrement = 1'b1; + end + end + + assign lineLoader_wayToAllocate_willClear = 1'b0; + assign lineLoader_wayToAllocate_willOverflowIfInc = 1'b1; + assign lineLoader_wayToAllocate_willOverflow = (lineLoader_wayToAllocate_willOverflowIfInc && lineLoader_wayToAllocate_willIncrement); + assign _zz_4_ = 1'b1; + assign lineLoader_write_tag_0_valid = ((_zz_4_ && lineLoader_fire) || (! lineLoader_flushCounter[5])); + assign lineLoader_write_tag_0_payload_address = (lineLoader_flushCounter[5] ? lineLoader_address[9 : 5] : lineLoader_flushCounter[4 : 0]); + assign lineLoader_write_tag_0_payload_data_valid = lineLoader_flushCounter[5]; + assign lineLoader_write_tag_0_payload_data_error = (lineLoader_hadError || io_mem_rsp_payload_error); + assign lineLoader_write_tag_0_payload_data_address = lineLoader_address[31 : 10]; + assign lineLoader_write_data_0_valid = (io_mem_rsp_valid && _zz_4_); + assign lineLoader_write_data_0_payload_address = {lineLoader_address[9 : 5],lineLoader_wordIndex}; + assign lineLoader_write_data_0_payload_data = io_mem_rsp_payload_data; + assign _zz_5_ = io_cpu_prefetch_pc[9 : 5]; + assign _zz_6_ = (! io_cpu_fetch_isStuck); + assign _zz_7_ = _zz_10_; + assign fetchStage_read_waysValues_0_tag_valid = _zz_14_[0]; + assign fetchStage_read_waysValues_0_tag_error = _zz_15_[0]; + assign fetchStage_read_waysValues_0_tag_address = _zz_7_[23 : 2]; + assign _zz_8_ = io_cpu_prefetch_pc[9 : 2]; + assign _zz_9_ = (! io_cpu_fetch_isStuck); + assign fetchStage_read_waysValues_0_data = _zz_11_; + assign fetchStage_hit_hits_0 = (fetchStage_read_waysValues_0_tag_valid && (fetchStage_read_waysValues_0_tag_address == io_cpu_fetch_mmuBus_rsp_physicalAddress[31 : 10])); + assign fetchStage_hit_valid = (fetchStage_hit_hits_0 != (1'b0)); + assign fetchStage_hit_error = fetchStage_read_waysValues_0_tag_error; + assign fetchStage_hit_data = fetchStage_read_waysValues_0_data; + assign fetchStage_hit_word = fetchStage_hit_data[31 : 0]; + assign io_cpu_fetch_data = (io_cpu_fetch_dataBypassValid ? io_cpu_fetch_dataBypass : fetchStage_hit_word); + assign io_cpu_fetch_mmuBus_cmd_isValid = io_cpu_fetch_isValid; + assign io_cpu_fetch_mmuBus_cmd_virtualAddress = io_cpu_fetch_pc; + assign io_cpu_fetch_mmuBus_cmd_bypassTranslation = 1'b0; + assign io_cpu_fetch_mmuBus_end = ((! io_cpu_fetch_isStuck) || io_cpu_fetch_isRemoved); + assign io_cpu_fetch_physicalAddress = io_cpu_fetch_mmuBus_rsp_physicalAddress; + assign io_cpu_fetch_cacheMiss = (! fetchStage_hit_valid); + assign io_cpu_fetch_error = fetchStage_hit_error; + assign io_cpu_fetch_mmuRefilling = io_cpu_fetch_mmuBus_rsp_refilling; + assign io_cpu_fetch_mmuException = ((! io_cpu_fetch_mmuBus_rsp_refilling) && (io_cpu_fetch_mmuBus_rsp_exception || (! io_cpu_fetch_mmuBus_rsp_allowExecute))); + always @ (posedge clk) begin + if(reset) begin + lineLoader_valid <= 1'b0; + lineLoader_hadError <= 1'b0; + lineLoader_flushPending <= 1'b1; + lineLoader_cmdSent <= 1'b0; + lineLoader_wordIndex <= (3'b000); + end else begin + if(lineLoader_fire)begin + lineLoader_valid <= 1'b0; + end + if(lineLoader_fire)begin + lineLoader_hadError <= 1'b0; + end + if(io_cpu_fill_valid)begin + lineLoader_valid <= 1'b1; + end + if(io_flush)begin + lineLoader_flushPending <= 1'b1; + end + if(_zz_13_)begin + lineLoader_flushPending <= 1'b0; + end + if((io_mem_cmd_valid && io_mem_cmd_ready))begin + lineLoader_cmdSent <= 1'b1; + end + if(lineLoader_fire)begin + lineLoader_cmdSent <= 1'b0; + end + if(io_mem_rsp_valid)begin + lineLoader_wordIndex <= (lineLoader_wordIndex + (3'b001)); + if(io_mem_rsp_payload_error)begin + lineLoader_hadError <= 1'b1; + end + end + end + end + + always @ (posedge clk) begin + if(io_cpu_fill_valid)begin + lineLoader_address <= io_cpu_fill_payload; + end + if(_zz_12_)begin + lineLoader_flushCounter <= (lineLoader_flushCounter + (6'b000001)); + end + _zz_3_ <= lineLoader_flushCounter[5]; + if(_zz_13_)begin + lineLoader_flushCounter <= (6'b000000); + end + end + +endmodule + +module VexRiscv ( + input [31:0] externalResetVector, + input timerInterrupt, + input softwareInterrupt, + input [31:0] externalInterruptArray, + output reg iBusWishbone_CYC, + output reg iBusWishbone_STB, + input iBusWishbone_ACK, + output iBusWishbone_WE, + output [29:0] iBusWishbone_ADR, + input [31:0] iBusWishbone_DAT_MISO, + output [31:0] iBusWishbone_DAT_MOSI, + output [3:0] iBusWishbone_SEL, + input iBusWishbone_ERR, + output [1:0] iBusWishbone_BTE, + output [2:0] iBusWishbone_CTI, + output dBusWishbone_CYC, + output dBusWishbone_STB, + input dBusWishbone_ACK, + output dBusWishbone_WE, + output [29:0] dBusWishbone_ADR, + input [31:0] dBusWishbone_DAT_MISO, + output [31:0] dBusWishbone_DAT_MOSI, + output reg [3:0] dBusWishbone_SEL, + input dBusWishbone_ERR, + output [1:0] dBusWishbone_BTE, + output [2:0] dBusWishbone_CTI, + input clk, + input reset); + wire _zz_130_; + wire _zz_131_; + wire _zz_132_; + wire _zz_133_; + wire _zz_134_; + wire [31:0] _zz_135_; + wire _zz_136_; + wire _zz_137_; + wire _zz_138_; + wire _zz_139_; + wire _zz_140_; + wire _zz_141_; + wire _zz_142_; + wire _zz_143_; + wire _zz_144_; + wire _zz_145_; + wire [31:0] _zz_146_; + reg _zz_147_; + reg [31:0] _zz_148_; + reg [31:0] _zz_149_; + reg [31:0] _zz_150_; + reg [3:0] _zz_151_; + reg [31:0] _zz_152_; + wire IBusCachedPlugin_cache_io_cpu_prefetch_haltIt; + wire IBusCachedPlugin_cache_io_cpu_fetch_error; + wire IBusCachedPlugin_cache_io_cpu_fetch_mmuRefilling; + wire IBusCachedPlugin_cache_io_cpu_fetch_mmuException; + wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_data; + wire IBusCachedPlugin_cache_io_cpu_fetch_cacheMiss; + wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress; + wire IBusCachedPlugin_cache_io_cpu_fetch_haltIt; + wire IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_isValid; + wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_virtualAddress; + wire IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_bypassTranslation; + wire IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_end; + wire [31:0] IBusCachedPlugin_cache_io_cpu_decode_data; + wire [31:0] IBusCachedPlugin_cache_io_cpu_decode_physicalAddress; + wire IBusCachedPlugin_cache_io_mem_cmd_valid; + wire [31:0] IBusCachedPlugin_cache_io_mem_cmd_payload_address; + wire [2:0] IBusCachedPlugin_cache_io_mem_cmd_payload_size; + wire _zz_153_; + wire _zz_154_; + wire _zz_155_; + wire _zz_156_; + wire _zz_157_; + wire _zz_158_; + wire [1:0] _zz_159_; + wire _zz_160_; + wire _zz_161_; + wire _zz_162_; + wire [1:0] _zz_163_; + wire _zz_164_; + wire [2:0] _zz_165_; + wire [2:0] _zz_166_; + wire [31:0] _zz_167_; + wire [2:0] _zz_168_; + wire [0:0] _zz_169_; + wire [0:0] _zz_170_; + wire [0:0] _zz_171_; + wire [0:0] _zz_172_; + wire [0:0] _zz_173_; + wire [0:0] _zz_174_; + wire [0:0] _zz_175_; + wire [0:0] _zz_176_; + wire [0:0] _zz_177_; + wire [2:0] _zz_178_; + wire [4:0] _zz_179_; + wire [11:0] _zz_180_; + wire [11:0] _zz_181_; + wire [31:0] _zz_182_; + wire [31:0] _zz_183_; + wire [31:0] _zz_184_; + wire [31:0] _zz_185_; + wire [31:0] _zz_186_; + wire [31:0] _zz_187_; + wire [31:0] _zz_188_; + wire [31:0] _zz_189_; + wire [32:0] _zz_190_; + wire [19:0] _zz_191_; + wire [11:0] _zz_192_; + wire [11:0] _zz_193_; + wire [1:0] _zz_194_; + wire [1:0] _zz_195_; + wire [2:0] _zz_196_; + wire [0:0] _zz_197_; + wire [0:0] _zz_198_; + wire [0:0] _zz_199_; + wire [0:0] _zz_200_; + wire [0:0] _zz_201_; + wire [0:0] _zz_202_; + wire [26:0] _zz_203_; + wire [6:0] _zz_204_; + wire [1:0] _zz_205_; + wire _zz_206_; + wire _zz_207_; + wire [0:0] _zz_208_; + wire [4:0] _zz_209_; + wire [0:0] _zz_210_; + wire [0:0] _zz_211_; + wire _zz_212_; + wire [0:0] _zz_213_; + wire [20:0] _zz_214_; + wire [31:0] _zz_215_; + wire [31:0] _zz_216_; + wire _zz_217_; + wire [0:0] _zz_218_; + wire [1:0] _zz_219_; + wire [31:0] _zz_220_; + wire [31:0] _zz_221_; + wire [31:0] _zz_222_; + wire [0:0] _zz_223_; + wire [1:0] _zz_224_; + wire [1:0] _zz_225_; + wire [1:0] _zz_226_; + wire _zz_227_; + wire [0:0] _zz_228_; + wire [17:0] _zz_229_; + wire [31:0] _zz_230_; + wire _zz_231_; + wire _zz_232_; + wire [31:0] _zz_233_; + wire [31:0] _zz_234_; + wire _zz_235_; + wire _zz_236_; + wire _zz_237_; + wire _zz_238_; + wire _zz_239_; + wire [0:0] _zz_240_; + wire [0:0] _zz_241_; + wire _zz_242_; + wire [0:0] _zz_243_; + wire [15:0] _zz_244_; + wire [31:0] _zz_245_; + wire [31:0] _zz_246_; + wire [31:0] _zz_247_; + wire [31:0] _zz_248_; + wire [31:0] _zz_249_; + wire [31:0] _zz_250_; + wire [31:0] _zz_251_; + wire [31:0] _zz_252_; + wire [31:0] _zz_253_; + wire [0:0] _zz_254_; + wire [0:0] _zz_255_; + wire [1:0] _zz_256_; + wire [1:0] _zz_257_; + wire _zz_258_; + wire [0:0] _zz_259_; + wire [13:0] _zz_260_; + wire [31:0] _zz_261_; + wire [31:0] _zz_262_; + wire [31:0] _zz_263_; + wire _zz_264_; + wire [0:0] _zz_265_; + wire [1:0] _zz_266_; + wire [0:0] _zz_267_; + wire [0:0] _zz_268_; + wire [1:0] _zz_269_; + wire [1:0] _zz_270_; + wire _zz_271_; + wire [0:0] _zz_272_; + wire [10:0] _zz_273_; + wire [31:0] _zz_274_; + wire [31:0] _zz_275_; + wire [31:0] _zz_276_; + wire _zz_277_; + wire _zz_278_; + wire [31:0] _zz_279_; + wire [31:0] _zz_280_; + wire [31:0] _zz_281_; + wire [31:0] _zz_282_; + wire _zz_283_; + wire _zz_284_; + wire [0:0] _zz_285_; + wire [0:0] _zz_286_; + wire _zz_287_; + wire [0:0] _zz_288_; + wire [8:0] _zz_289_; + wire [31:0] _zz_290_; + wire _zz_291_; + wire _zz_292_; + wire [0:0] _zz_293_; + wire [0:0] _zz_294_; + wire [0:0] _zz_295_; + wire [0:0] _zz_296_; + wire _zz_297_; + wire [0:0] _zz_298_; + wire [5:0] _zz_299_; + wire [31:0] _zz_300_; + wire [31:0] _zz_301_; + wire [31:0] _zz_302_; + wire [31:0] _zz_303_; + wire [31:0] _zz_304_; + wire [0:0] _zz_305_; + wire [0:0] _zz_306_; + wire [1:0] _zz_307_; + wire [1:0] _zz_308_; + wire _zz_309_; + wire [0:0] _zz_310_; + wire [2:0] _zz_311_; + wire [31:0] _zz_312_; + wire [31:0] _zz_313_; + wire _zz_314_; + wire _zz_315_; + wire _zz_316_; + wire [0:0] _zz_317_; + wire [0:0] _zz_318_; + wire [1:0] _zz_319_; + wire [1:0] _zz_320_; + wire [31:0] _zz_321_; + wire [31:0] _zz_322_; + wire [31:0] _zz_323_; + wire _zz_324_; + wire [0:0] _zz_325_; + wire [12:0] _zz_326_; + wire [31:0] _zz_327_; + wire [31:0] _zz_328_; + wire [31:0] _zz_329_; + wire _zz_330_; + wire [0:0] _zz_331_; + wire [6:0] _zz_332_; + wire [31:0] _zz_333_; + wire [31:0] _zz_334_; + wire [31:0] _zz_335_; + wire _zz_336_; + wire [0:0] _zz_337_; + wire [0:0] _zz_338_; + wire decode_CSR_WRITE_OPCODE; + wire decode_SRC_LESS_UNSIGNED; + wire `EnvCtrlEnum_defaultEncoding_type decode_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_1_; + wire `EnvCtrlEnum_defaultEncoding_type _zz_2_; + wire `EnvCtrlEnum_defaultEncoding_type _zz_3_; + wire [31:0] execute_FORMAL_PC_NEXT; + wire [31:0] decode_FORMAL_PC_NEXT; + wire `Src2CtrlEnum_defaultEncoding_type decode_SRC2_CTRL; + wire `Src2CtrlEnum_defaultEncoding_type _zz_4_; + wire `Src2CtrlEnum_defaultEncoding_type _zz_5_; + wire `Src2CtrlEnum_defaultEncoding_type _zz_6_; + wire decode_IS_CSR; + wire decode_MEMORY_ENABLE; + wire `Src1CtrlEnum_defaultEncoding_type decode_SRC1_CTRL; + wire `Src1CtrlEnum_defaultEncoding_type _zz_7_; + wire `Src1CtrlEnum_defaultEncoding_type _zz_8_; + wire `Src1CtrlEnum_defaultEncoding_type _zz_9_; + wire decode_CSR_READ_OPCODE; + wire execute_REGFILE_WRITE_VALID; + wire `AluCtrlEnum_defaultEncoding_type decode_ALU_CTRL; + wire `AluCtrlEnum_defaultEncoding_type _zz_10_; + wire `AluCtrlEnum_defaultEncoding_type _zz_11_; + wire `AluCtrlEnum_defaultEncoding_type _zz_12_; + wire decode_SRC2_FORCE_ZERO; + wire decode_MEMORY_STORE; + wire `BranchCtrlEnum_defaultEncoding_type decode_BRANCH_CTRL; + wire `BranchCtrlEnum_defaultEncoding_type _zz_13_; + wire `BranchCtrlEnum_defaultEncoding_type _zz_14_; + wire `BranchCtrlEnum_defaultEncoding_type _zz_15_; + wire `ShiftCtrlEnum_defaultEncoding_type decode_SHIFT_CTRL; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_16_; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_17_; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_18_; + wire `AluBitwiseCtrlEnum_defaultEncoding_type decode_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_19_; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_20_; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_21_; + wire execute_CSR_READ_OPCODE; + wire execute_CSR_WRITE_OPCODE; + wire execute_IS_CSR; + wire _zz_22_; + wire _zz_23_; + wire `EnvCtrlEnum_defaultEncoding_type execute_ENV_CTRL; + wire `EnvCtrlEnum_defaultEncoding_type _zz_24_; + wire [31:0] execute_BRANCH_CALC; + wire execute_BRANCH_DO; + wire [31:0] _zz_25_; + wire [31:0] execute_PC; + wire [31:0] execute_RS1; + wire `BranchCtrlEnum_defaultEncoding_type execute_BRANCH_CTRL; + wire `BranchCtrlEnum_defaultEncoding_type _zz_26_; + wire _zz_27_; + wire `ShiftCtrlEnum_defaultEncoding_type execute_SHIFT_CTRL; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_28_; + wire _zz_29_; + wire [31:0] _zz_30_; + wire [31:0] _zz_31_; + wire execute_SRC_LESS_UNSIGNED; + wire execute_SRC2_FORCE_ZERO; + wire execute_SRC_USE_SUB_LESS; + wire `Src2CtrlEnum_defaultEncoding_type execute_SRC2_CTRL; + wire `Src2CtrlEnum_defaultEncoding_type _zz_32_; + wire [31:0] _zz_33_; + wire `Src1CtrlEnum_defaultEncoding_type execute_SRC1_CTRL; + wire `Src1CtrlEnum_defaultEncoding_type _zz_34_; + wire [31:0] _zz_35_; + wire decode_SRC_USE_SUB_LESS; + wire decode_SRC_ADD_ZERO; + wire _zz_36_; + wire [31:0] execute_SRC_ADD_SUB; + wire execute_SRC_LESS; + wire `AluCtrlEnum_defaultEncoding_type execute_ALU_CTRL; + wire `AluCtrlEnum_defaultEncoding_type _zz_37_; + wire [31:0] _zz_38_; + wire [31:0] execute_SRC2; + wire [31:0] execute_SRC1; + wire `AluBitwiseCtrlEnum_defaultEncoding_type execute_ALU_BITWISE_CTRL; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_39_; + reg _zz_40_; + wire [31:0] _zz_41_; + wire [31:0] _zz_42_; + reg decode_REGFILE_WRITE_VALID; + wire decode_LEGAL_INSTRUCTION; + wire decode_INSTRUCTION_READY; + wire _zz_43_; + wire _zz_44_; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_45_; + wire _zz_46_; + wire _zz_47_; + wire _zz_48_; + wire _zz_49_; + wire `Src1CtrlEnum_defaultEncoding_type _zz_50_; + wire `BranchCtrlEnum_defaultEncoding_type _zz_51_; + wire `EnvCtrlEnum_defaultEncoding_type _zz_52_; + wire `AluCtrlEnum_defaultEncoding_type _zz_53_; + wire _zz_54_; + wire `Src2CtrlEnum_defaultEncoding_type _zz_55_; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_56_; + wire _zz_57_; + wire _zz_58_; + reg [31:0] _zz_59_; + wire [1:0] execute_MEMORY_ADDRESS_LOW; + wire [31:0] execute_MEMORY_READ_DATA; + wire [31:0] execute_REGFILE_WRITE_DATA; + wire [31:0] _zz_60_; + wire [31:0] execute_SRC_ADD; + wire [1:0] _zz_61_; + wire [31:0] execute_RS2; + wire [31:0] execute_INSTRUCTION; + wire execute_MEMORY_STORE; + wire execute_MEMORY_ENABLE; + wire execute_ALIGNEMENT_FAULT; + wire _zz_62_; + wire decode_FLUSH_ALL; + reg IBusCachedPlugin_rsp_issueDetected; + reg _zz_63_; + reg _zz_64_; + reg _zz_65_; + reg [31:0] _zz_66_; + wire [31:0] _zz_67_; + wire [31:0] _zz_68_; + wire [31:0] _zz_69_; + wire [31:0] decode_PC /* verilator public */ ; + wire [31:0] decode_INSTRUCTION /* verilator public */ ; + wire decode_arbitration_haltItself /* verilator public */ ; + reg decode_arbitration_haltByOther; + reg decode_arbitration_removeIt; + reg decode_arbitration_flushAll /* verilator public */ ; + wire decode_arbitration_isValid /* verilator public */ ; + wire decode_arbitration_isStuck; + wire decode_arbitration_isStuckByOthers; + wire decode_arbitration_isFlushed; + wire decode_arbitration_isMoving; + wire decode_arbitration_isFiring; + reg execute_arbitration_haltItself; + wire execute_arbitration_haltByOther; + reg execute_arbitration_removeIt; + wire execute_arbitration_flushAll; + reg execute_arbitration_isValid; + wire execute_arbitration_isStuck; + wire execute_arbitration_isStuckByOthers; + wire execute_arbitration_isFlushed; + wire execute_arbitration_isMoving; + wire execute_arbitration_isFiring; + reg IBusCachedPlugin_fetcherHalt; + wire IBusCachedPlugin_fetcherflushIt; + reg IBusCachedPlugin_incomingInstruction; + wire IBusCachedPlugin_pcValids_0; + wire IBusCachedPlugin_pcValids_1; + wire IBusCachedPlugin_redoBranch_valid; + wire [31:0] IBusCachedPlugin_redoBranch_payload; + reg IBusCachedPlugin_decodeExceptionPort_valid; + reg [3:0] IBusCachedPlugin_decodeExceptionPort_payload_code; + wire [31:0] IBusCachedPlugin_decodeExceptionPort_payload_badAddr; + reg DBusSimplePlugin_memoryExceptionPort_valid; + reg [3:0] DBusSimplePlugin_memoryExceptionPort_payload_code; + wire [31:0] DBusSimplePlugin_memoryExceptionPort_payload_badAddr; + wire decodeExceptionPort_valid; + wire [3:0] decodeExceptionPort_payload_code; + wire [31:0] decodeExceptionPort_payload_badAddr; + wire BranchPlugin_jumpInterface_valid; + wire [31:0] BranchPlugin_jumpInterface_payload; + reg BranchPlugin_branchExceptionPort_valid; + wire [3:0] BranchPlugin_branchExceptionPort_payload_code; + wire [31:0] BranchPlugin_branchExceptionPort_payload_badAddr; + reg CsrPlugin_jumpInterface_valid; + reg [31:0] CsrPlugin_jumpInterface_payload; + wire CsrPlugin_exceptionPendings_0; + wire CsrPlugin_exceptionPendings_1; + wire externalInterrupt; + wire contextSwitching; + reg [1:0] CsrPlugin_privilege; + wire CsrPlugin_forceMachineWire; + reg CsrPlugin_selfException_valid; + reg [3:0] CsrPlugin_selfException_payload_code; + wire [31:0] CsrPlugin_selfException_payload_badAddr; + wire CsrPlugin_allowInterrupts; + wire CsrPlugin_allowException; + wire IBusCachedPlugin_jump_pcLoad_valid; + wire [31:0] IBusCachedPlugin_jump_pcLoad_payload; + wire [2:0] _zz_70_; + wire [2:0] _zz_71_; + wire _zz_72_; + wire _zz_73_; + wire IBusCachedPlugin_fetchPc_preOutput_valid; + wire IBusCachedPlugin_fetchPc_preOutput_ready; + wire [31:0] IBusCachedPlugin_fetchPc_preOutput_payload; + wire _zz_74_; + wire IBusCachedPlugin_fetchPc_output_valid; + wire IBusCachedPlugin_fetchPc_output_ready; + wire [31:0] IBusCachedPlugin_fetchPc_output_payload; + reg [31:0] IBusCachedPlugin_fetchPc_pcReg /* verilator public */ ; + reg IBusCachedPlugin_fetchPc_inc; + reg IBusCachedPlugin_fetchPc_propagatePc; + reg [31:0] IBusCachedPlugin_fetchPc_pc; + reg IBusCachedPlugin_fetchPc_samplePcNext; + reg _zz_75_; + wire IBusCachedPlugin_iBusRsp_stages_0_input_valid; + wire IBusCachedPlugin_iBusRsp_stages_0_input_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_0_input_payload; + wire IBusCachedPlugin_iBusRsp_stages_0_output_valid; + wire IBusCachedPlugin_iBusRsp_stages_0_output_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_0_output_payload; + reg IBusCachedPlugin_iBusRsp_stages_0_halt; + wire IBusCachedPlugin_iBusRsp_stages_0_inputSample; + wire IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid; + wire IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload; + wire IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_valid; + wire IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_payload; + reg IBusCachedPlugin_iBusRsp_cacheRspArbitration_halt; + wire IBusCachedPlugin_iBusRsp_cacheRspArbitration_inputSample; + wire _zz_76_; + wire _zz_77_; + wire _zz_78_; + wire _zz_79_; + reg _zz_80_; + reg IBusCachedPlugin_iBusRsp_readyForError; + wire IBusCachedPlugin_iBusRsp_decodeInput_valid; + wire IBusCachedPlugin_iBusRsp_decodeInput_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_decodeInput_payload_pc; + wire IBusCachedPlugin_iBusRsp_decodeInput_payload_rsp_error; + wire [31:0] IBusCachedPlugin_iBusRsp_decodeInput_payload_rsp_inst; + wire IBusCachedPlugin_iBusRsp_decodeInput_payload_isRvc; + reg IBusCachedPlugin_injector_nextPcCalc_valids_0; + reg IBusCachedPlugin_injector_nextPcCalc_valids_1; + reg IBusCachedPlugin_injector_decodeRemoved; + wire iBus_cmd_valid; + wire iBus_cmd_ready; + reg [31:0] iBus_cmd_payload_address; + wire [2:0] iBus_cmd_payload_size; + wire iBus_rsp_valid; + wire [31:0] iBus_rsp_payload_data; + wire iBus_rsp_payload_error; + wire IBusCachedPlugin_s0_tightlyCoupledHit; + reg IBusCachedPlugin_s1_tightlyCoupledHit; + wire IBusCachedPlugin_rsp_iBusRspOutputHalt; + reg IBusCachedPlugin_rsp_redoFetch; + wire dBus_cmd_valid; + wire dBus_cmd_ready; + wire dBus_cmd_payload_wr; + wire [31:0] dBus_cmd_payload_address; + wire [31:0] dBus_cmd_payload_data; + wire [1:0] dBus_cmd_payload_size; + wire dBus_rsp_ready; + wire dBus_rsp_error; + wire [31:0] dBus_rsp_data; + reg execute_DBusSimplePlugin_cmdSent; + reg execute_DBusSimplePlugin_skipCmd; + reg [31:0] _zz_81_; + reg [3:0] _zz_82_; + wire [3:0] execute_DBusSimplePlugin_formalMask; + reg [31:0] execute_DBusSimplePlugin_rspShifted; + wire _zz_83_; + reg [31:0] _zz_84_; + wire _zz_85_; + reg [31:0] _zz_86_; + reg [31:0] execute_DBusSimplePlugin_rspFormated; + wire [26:0] _zz_87_; + wire _zz_88_; + wire _zz_89_; + wire _zz_90_; + wire _zz_91_; + wire `ShiftCtrlEnum_defaultEncoding_type _zz_92_; + wire `Src2CtrlEnum_defaultEncoding_type _zz_93_; + wire `AluCtrlEnum_defaultEncoding_type _zz_94_; + wire `EnvCtrlEnum_defaultEncoding_type _zz_95_; + wire `BranchCtrlEnum_defaultEncoding_type _zz_96_; + wire `Src1CtrlEnum_defaultEncoding_type _zz_97_; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_98_; + wire [4:0] execute_RegFilePlugin_regFileReadAddress1; + wire [4:0] execute_RegFilePlugin_regFileReadAddress2; + wire _zz_99_; + wire [31:0] execute_RegFilePlugin_rs1Data; + wire [31:0] execute_RegFilePlugin_rs2Data; + wire execute_RegFilePlugin_regFileWrite_valid /* verilator public */ ; + wire [4:0] execute_RegFilePlugin_regFileWrite_payload_address /* verilator public */ ; + wire [31:0] execute_RegFilePlugin_regFileWrite_payload_data /* verilator public */ ; + reg [31:0] execute_IntAluPlugin_bitwise; + reg [31:0] _zz_100_; + reg [31:0] _zz_101_; + wire _zz_102_; + reg [19:0] _zz_103_; + wire _zz_104_; + reg [19:0] _zz_105_; + reg [31:0] _zz_106_; + reg [31:0] execute_SrcPlugin_addSub; + wire execute_SrcPlugin_less; + reg execute_LightShifterPlugin_isActive; + wire execute_LightShifterPlugin_isShift; + reg [4:0] execute_LightShifterPlugin_amplitudeReg; + wire [4:0] execute_LightShifterPlugin_amplitude; + reg [31:0] execute_LightShifterPlugin_shiftReg; + wire [31:0] execute_LightShifterPlugin_shiftInput; + wire execute_LightShifterPlugin_done; + reg [31:0] _zz_107_; + wire execute_BranchPlugin_eq; + wire [2:0] _zz_108_; + reg _zz_109_; + reg _zz_110_; + wire [31:0] execute_BranchPlugin_branch_src1; + wire _zz_111_; + reg [10:0] _zz_112_; + wire _zz_113_; + reg [19:0] _zz_114_; + wire _zz_115_; + reg [18:0] _zz_116_; + reg [31:0] _zz_117_; + wire [31:0] execute_BranchPlugin_branch_src2; + wire [31:0] execute_BranchPlugin_branchAdder; + wire [1:0] CsrPlugin_misa_base; + wire [25:0] CsrPlugin_misa_extensions; + reg [1:0] CsrPlugin_mtvec_mode; + reg [29:0] CsrPlugin_mtvec_base; + reg [31:0] CsrPlugin_mepc; + reg CsrPlugin_mstatus_MIE; + reg CsrPlugin_mstatus_MPIE; + reg [1:0] CsrPlugin_mstatus_MPP; + reg CsrPlugin_mip_MEIP; + reg CsrPlugin_mip_MTIP; + reg CsrPlugin_mip_MSIP; + reg CsrPlugin_mie_MEIE; + reg CsrPlugin_mie_MTIE; + reg CsrPlugin_mie_MSIE; + reg [31:0] CsrPlugin_mscratch; + reg CsrPlugin_mcause_interrupt; + reg [3:0] CsrPlugin_mcause_exceptionCode; + reg [31:0] CsrPlugin_mtval; + reg [63:0] CsrPlugin_mcycle = 64'b0000000000000000000000000000000000000000000000000000000000000000; + reg [63:0] CsrPlugin_minstret = 64'b0000000000000000000000000000000000000000000000000000000000000000; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_decode; + reg CsrPlugin_exceptionPortCtrl_exceptionValids_execute; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; + reg CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; + reg [3:0] CsrPlugin_exceptionPortCtrl_exceptionContext_code; + reg [31:0] CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; + wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped; + wire [1:0] CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; + wire [1:0] _zz_118_; + wire _zz_119_; + wire [2:0] _zz_120_; + wire [2:0] _zz_121_; + wire _zz_122_; + wire _zz_123_; + wire [1:0] _zz_124_; + reg CsrPlugin_interrupt; + reg [3:0] CsrPlugin_interruptCode /* verilator public */ ; + reg [1:0] CsrPlugin_interruptTargetPrivilege; + wire CsrPlugin_exception; + wire CsrPlugin_lastStageWasWfi; + reg CsrPlugin_pipelineLiberator_done; + wire CsrPlugin_interruptJump /* verilator public */ ; + reg CsrPlugin_hadException; + reg [1:0] CsrPlugin_targetPrivilege; + reg [3:0] CsrPlugin_trapCause; + reg [1:0] CsrPlugin_xtvec_mode; + reg [29:0] CsrPlugin_xtvec_base; + wire execute_CsrPlugin_inWfi /* verilator public */ ; + wire execute_CsrPlugin_blockedBySideEffects; + reg execute_CsrPlugin_illegalAccess; + reg execute_CsrPlugin_illegalInstruction; + reg [31:0] execute_CsrPlugin_readData; + wire execute_CsrPlugin_writeInstruction; + wire execute_CsrPlugin_readInstruction; + wire execute_CsrPlugin_writeEnable; + wire execute_CsrPlugin_readEnable; + wire [31:0] execute_CsrPlugin_readToWriteData; + reg [31:0] execute_CsrPlugin_writeData; + wire [11:0] execute_CsrPlugin_csrAddress; + reg [31:0] _zz_125_; + reg [31:0] externalInterruptArray_regNext; + wire [31:0] _zz_126_; + reg `AluBitwiseCtrlEnum_defaultEncoding_type decode_to_execute_ALU_BITWISE_CTRL; + reg `ShiftCtrlEnum_defaultEncoding_type decode_to_execute_SHIFT_CTRL; + reg `BranchCtrlEnum_defaultEncoding_type decode_to_execute_BRANCH_CTRL; + reg decode_to_execute_MEMORY_STORE; + reg decode_to_execute_SRC2_FORCE_ZERO; + reg `AluCtrlEnum_defaultEncoding_type decode_to_execute_ALU_CTRL; + reg decode_to_execute_SRC_USE_SUB_LESS; + reg decode_to_execute_REGFILE_WRITE_VALID; + reg decode_to_execute_CSR_READ_OPCODE; + reg `Src1CtrlEnum_defaultEncoding_type decode_to_execute_SRC1_CTRL; + reg decode_to_execute_MEMORY_ENABLE; + reg decode_to_execute_IS_CSR; + reg `Src2CtrlEnum_defaultEncoding_type decode_to_execute_SRC2_CTRL; + reg [31:0] decode_to_execute_PC; + reg [31:0] decode_to_execute_INSTRUCTION; + reg [31:0] decode_to_execute_FORMAL_PC_NEXT; + reg `EnvCtrlEnum_defaultEncoding_type decode_to_execute_ENV_CTRL; + reg decode_to_execute_SRC_LESS_UNSIGNED; + reg decode_to_execute_CSR_WRITE_OPCODE; + reg [2:0] _zz_127_; + reg _zz_128_; + reg [31:0] iBusWishbone_DAT_MISO_regNext; + wire dBus_cmd_halfPipe_valid; + wire dBus_cmd_halfPipe_ready; + wire dBus_cmd_halfPipe_payload_wr; + wire [31:0] dBus_cmd_halfPipe_payload_address; + wire [31:0] dBus_cmd_halfPipe_payload_data; + wire [1:0] dBus_cmd_halfPipe_payload_size; + reg dBus_cmd_halfPipe_regs_valid; + reg dBus_cmd_halfPipe_regs_ready; + reg dBus_cmd_halfPipe_regs_payload_wr; + reg [31:0] dBus_cmd_halfPipe_regs_payload_address; + reg [31:0] dBus_cmd_halfPipe_regs_payload_data; + reg [1:0] dBus_cmd_halfPipe_regs_payload_size; + reg [3:0] _zz_129_; + `ifndef SYNTHESIS + reg [47:0] decode_ENV_CTRL_string; + reg [47:0] _zz_1__string; + reg [47:0] _zz_2__string; + reg [47:0] _zz_3__string; + reg [23:0] decode_SRC2_CTRL_string; + reg [23:0] _zz_4__string; + reg [23:0] _zz_5__string; + reg [23:0] _zz_6__string; + reg [95:0] decode_SRC1_CTRL_string; + reg [95:0] _zz_7__string; + reg [95:0] _zz_8__string; + reg [95:0] _zz_9__string; + reg [63:0] decode_ALU_CTRL_string; + reg [63:0] _zz_10__string; + reg [63:0] _zz_11__string; + reg [63:0] _zz_12__string; + reg [31:0] decode_BRANCH_CTRL_string; + reg [31:0] _zz_13__string; + reg [31:0] _zz_14__string; + reg [31:0] _zz_15__string; + reg [71:0] decode_SHIFT_CTRL_string; + reg [71:0] _zz_16__string; + reg [71:0] _zz_17__string; + reg [71:0] _zz_18__string; + reg [39:0] decode_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_19__string; + reg [39:0] _zz_20__string; + reg [39:0] _zz_21__string; + reg [47:0] execute_ENV_CTRL_string; + reg [47:0] _zz_24__string; + reg [31:0] execute_BRANCH_CTRL_string; + reg [31:0] _zz_26__string; + reg [71:0] execute_SHIFT_CTRL_string; + reg [71:0] _zz_28__string; + reg [23:0] execute_SRC2_CTRL_string; + reg [23:0] _zz_32__string; + reg [95:0] execute_SRC1_CTRL_string; + reg [95:0] _zz_34__string; + reg [63:0] execute_ALU_CTRL_string; + reg [63:0] _zz_37__string; + reg [39:0] execute_ALU_BITWISE_CTRL_string; + reg [39:0] _zz_39__string; + reg [39:0] _zz_45__string; + reg [95:0] _zz_50__string; + reg [31:0] _zz_51__string; + reg [47:0] _zz_52__string; + reg [63:0] _zz_53__string; + reg [23:0] _zz_55__string; + reg [71:0] _zz_56__string; + reg [71:0] _zz_92__string; + reg [23:0] _zz_93__string; + reg [63:0] _zz_94__string; + reg [47:0] _zz_95__string; + reg [31:0] _zz_96__string; + reg [95:0] _zz_97__string; + reg [39:0] _zz_98__string; + reg [39:0] decode_to_execute_ALU_BITWISE_CTRL_string; + reg [71:0] decode_to_execute_SHIFT_CTRL_string; + reg [31:0] decode_to_execute_BRANCH_CTRL_string; + reg [63:0] decode_to_execute_ALU_CTRL_string; + reg [95:0] decode_to_execute_SRC1_CTRL_string; + reg [23:0] decode_to_execute_SRC2_CTRL_string; + reg [47:0] decode_to_execute_ENV_CTRL_string; + `endif + + reg [31:0] RegFilePlugin_regFile [0:31] /* verilator public */ ; + assign _zz_153_ = ((execute_arbitration_isValid && execute_LightShifterPlugin_isShift) && (execute_SRC2[4 : 0] != (5'b00000))); + assign _zz_154_ = (! execute_arbitration_isStuckByOthers); + assign _zz_155_ = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != (2'b00)); + assign _zz_156_ = ({CsrPlugin_selfException_valid,{BranchPlugin_branchExceptionPort_valid,DBusSimplePlugin_memoryExceptionPort_valid}} != (3'b000)); + assign _zz_157_ = (CsrPlugin_hadException || CsrPlugin_interruptJump); + assign _zz_158_ = (execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)); + assign _zz_159_ = execute_INSTRUCTION[29 : 28]; + assign _zz_160_ = (IBusCachedPlugin_fetchPc_preOutput_valid && IBusCachedPlugin_fetchPc_preOutput_ready); + assign _zz_161_ = (iBus_cmd_valid || (_zz_127_ != (3'b000))); + assign _zz_162_ = (! dBus_cmd_halfPipe_regs_valid); + assign _zz_163_ = execute_INSTRUCTION[13 : 12]; + assign _zz_164_ = execute_INSTRUCTION[13]; + assign _zz_165_ = (_zz_70_ - (3'b001)); + assign _zz_166_ = {IBusCachedPlugin_fetchPc_inc,(2'b00)}; + assign _zz_167_ = {29'd0, _zz_166_}; + assign _zz_168_ = (execute_MEMORY_STORE ? (3'b110) : (3'b100)); + assign _zz_169_ = _zz_87_[0 : 0]; + assign _zz_170_ = _zz_87_[7 : 7]; + assign _zz_171_ = _zz_87_[18 : 18]; + assign _zz_172_ = _zz_87_[19 : 19]; + assign _zz_173_ = _zz_87_[20 : 20]; + assign _zz_174_ = _zz_87_[21 : 21]; + assign _zz_175_ = _zz_87_[24 : 24]; + assign _zz_176_ = _zz_87_[25 : 25]; + assign _zz_177_ = execute_SRC_LESS; + assign _zz_178_ = (3'b100); + assign _zz_179_ = execute_INSTRUCTION[19 : 15]; + assign _zz_180_ = execute_INSTRUCTION[31 : 20]; + assign _zz_181_ = {execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}; + assign _zz_182_ = ($signed(_zz_183_) + $signed(_zz_186_)); + assign _zz_183_ = ($signed(_zz_184_) + $signed(_zz_185_)); + assign _zz_184_ = execute_SRC1; + assign _zz_185_ = (execute_SRC_USE_SUB_LESS ? (~ execute_SRC2) : execute_SRC2); + assign _zz_186_ = (execute_SRC_USE_SUB_LESS ? _zz_187_ : _zz_188_); + assign _zz_187_ = (32'b00000000000000000000000000000001); + assign _zz_188_ = (32'b00000000000000000000000000000000); + assign _zz_189_ = (_zz_190_ >>> 1); + assign _zz_190_ = {((execute_SHIFT_CTRL == `ShiftCtrlEnum_defaultEncoding_SRA_1) && execute_LightShifterPlugin_shiftInput[31]),execute_LightShifterPlugin_shiftInput}; + assign _zz_191_ = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}; + assign _zz_192_ = execute_INSTRUCTION[31 : 20]; + assign _zz_193_ = {{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}; + assign _zz_194_ = (_zz_118_ & (~ _zz_195_)); + assign _zz_195_ = (_zz_118_ - (2'b01)); + assign _zz_196_ = (_zz_120_ - (3'b001)); + assign _zz_197_ = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_198_ = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_199_ = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_200_ = execute_CsrPlugin_writeData[11 : 11]; + assign _zz_201_ = execute_CsrPlugin_writeData[7 : 7]; + assign _zz_202_ = execute_CsrPlugin_writeData[3 : 3]; + assign _zz_203_ = (iBus_cmd_payload_address >>> 5); + assign _zz_204_ = ({3'd0,_zz_129_} <<< dBus_cmd_halfPipe_payload_address[1 : 0]); + assign _zz_205_ = {_zz_73_,_zz_72_}; + assign _zz_206_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001100100)) == (32'b00000000000000000000000000100100)); + assign _zz_207_ = ((decode_INSTRUCTION & (32'b00000000000000000011000001010100)) == (32'b00000000000000000001000000010000)); + assign _zz_208_ = _zz_89_; + assign _zz_209_ = {(_zz_215_ == _zz_216_),{_zz_217_,{_zz_218_,_zz_219_}}}; + assign _zz_210_ = ((decode_INSTRUCTION & _zz_220_) == (32'b00000000000000000001000000000000)); + assign _zz_211_ = (1'b0); + assign _zz_212_ = ((_zz_221_ == _zz_222_) != (1'b0)); + assign _zz_213_ = ({_zz_223_,_zz_224_} != (3'b000)); + assign _zz_214_ = {(_zz_225_ != _zz_226_),{_zz_227_,{_zz_228_,_zz_229_}}}; + assign _zz_215_ = (decode_INSTRUCTION & (32'b00000000000000000001000000010000)); + assign _zz_216_ = (32'b00000000000000000001000000010000); + assign _zz_217_ = ((decode_INSTRUCTION & _zz_230_) == (32'b00000000000000000010000000010000)); + assign _zz_218_ = _zz_91_; + assign _zz_219_ = {_zz_231_,_zz_232_}; + assign _zz_220_ = (32'b00000000000000000001000000000000); + assign _zz_221_ = (decode_INSTRUCTION & (32'b00000000000000000011000000000000)); + assign _zz_222_ = (32'b00000000000000000010000000000000); + assign _zz_223_ = (_zz_233_ == _zz_234_); + assign _zz_224_ = {_zz_235_,_zz_236_}; + assign _zz_225_ = {_zz_237_,_zz_238_}; + assign _zz_226_ = (2'b00); + assign _zz_227_ = (_zz_239_ != (1'b0)); + assign _zz_228_ = (_zz_240_ != _zz_241_); + assign _zz_229_ = {_zz_242_,{_zz_243_,_zz_244_}}; + assign _zz_230_ = (32'b00000000000000000010000000010000); + assign _zz_231_ = ((decode_INSTRUCTION & _zz_245_) == (32'b00000000000000000000000000000100)); + assign _zz_232_ = ((decode_INSTRUCTION & _zz_246_) == (32'b00000000000000000000000000000000)); + assign _zz_233_ = (decode_INSTRUCTION & (32'b00000000000000000000000001000100)); + assign _zz_234_ = (32'b00000000000000000000000001000000); + assign _zz_235_ = ((decode_INSTRUCTION & _zz_247_) == (32'b00000000000000000010000000010000)); + assign _zz_236_ = ((decode_INSTRUCTION & _zz_248_) == (32'b01000000000000000000000000110000)); + assign _zz_237_ = ((decode_INSTRUCTION & _zz_249_) == (32'b00000000000000000010000000000000)); + assign _zz_238_ = ((decode_INSTRUCTION & _zz_250_) == (32'b00000000000000000001000000000000)); + assign _zz_239_ = ((decode_INSTRUCTION & _zz_251_) == (32'b00000000000000000000000000100000)); + assign _zz_240_ = (_zz_252_ == _zz_253_); + assign _zz_241_ = (1'b0); + assign _zz_242_ = ({_zz_254_,_zz_255_} != (2'b00)); + assign _zz_243_ = (_zz_256_ != _zz_257_); + assign _zz_244_ = {_zz_258_,{_zz_259_,_zz_260_}}; + assign _zz_245_ = (32'b00000000000000000000000000001100); + assign _zz_246_ = (32'b00000000000000000000000000101000); + assign _zz_247_ = (32'b00000000000000000010000000010100); + assign _zz_248_ = (32'b01000000000000000100000000110100); + assign _zz_249_ = (32'b00000000000000000010000000010000); + assign _zz_250_ = (32'b00000000000000000101000000000000); + assign _zz_251_ = (32'b00000000000000000000000000100000); + assign _zz_252_ = (decode_INSTRUCTION & (32'b00000000000000000000000001011000)); + assign _zz_253_ = (32'b00000000000000000000000000000000); + assign _zz_254_ = ((decode_INSTRUCTION & _zz_261_) == (32'b00000000000000000000000000000100)); + assign _zz_255_ = _zz_90_; + assign _zz_256_ = {(_zz_262_ == _zz_263_),_zz_90_}; + assign _zz_257_ = (2'b00); + assign _zz_258_ = ({_zz_264_,{_zz_265_,_zz_266_}} != (4'b0000)); + assign _zz_259_ = ({_zz_267_,_zz_268_} != (2'b00)); + assign _zz_260_ = {(_zz_269_ != _zz_270_),{_zz_271_,{_zz_272_,_zz_273_}}}; + assign _zz_261_ = (32'b00000000000000000000000000010100); + assign _zz_262_ = (decode_INSTRUCTION & (32'b00000000000000000000000001000100)); + assign _zz_263_ = (32'b00000000000000000000000000000100); + assign _zz_264_ = ((decode_INSTRUCTION & _zz_274_) == (32'b00000000000000000000000000000000)); + assign _zz_265_ = (_zz_275_ == _zz_276_); + assign _zz_266_ = {_zz_277_,_zz_278_}; + assign _zz_267_ = (_zz_279_ == _zz_280_); + assign _zz_268_ = (_zz_281_ == _zz_282_); + assign _zz_269_ = {_zz_89_,_zz_283_}; + assign _zz_270_ = (2'b00); + assign _zz_271_ = (_zz_284_ != (1'b0)); + assign _zz_272_ = (_zz_285_ != _zz_286_); + assign _zz_273_ = {_zz_287_,{_zz_288_,_zz_289_}}; + assign _zz_274_ = (32'b00000000000000000000000001000100); + assign _zz_275_ = (decode_INSTRUCTION & (32'b00000000000000000000000000011000)); + assign _zz_276_ = (32'b00000000000000000000000000000000); + assign _zz_277_ = ((decode_INSTRUCTION & (32'b00000000000000000110000000000100)) == (32'b00000000000000000010000000000000)); + assign _zz_278_ = ((decode_INSTRUCTION & (32'b00000000000000000101000000000100)) == (32'b00000000000000000001000000000000)); + assign _zz_279_ = (decode_INSTRUCTION & (32'b00000000000000000000000000110100)); + assign _zz_280_ = (32'b00000000000000000000000000100000); + assign _zz_281_ = (decode_INSTRUCTION & (32'b00000000000000000000000001100100)); + assign _zz_282_ = (32'b00000000000000000000000000100000); + assign _zz_283_ = ((decode_INSTRUCTION & (32'b00000000000000000000000000011100)) == (32'b00000000000000000000000000000100)); + assign _zz_284_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001011000)) == (32'b00000000000000000000000001000000)); + assign _zz_285_ = ((decode_INSTRUCTION & _zz_290_) == (32'b00000000000000000000000001010000)); + assign _zz_286_ = (1'b0); + assign _zz_287_ = ({_zz_291_,_zz_292_} != (2'b00)); + assign _zz_288_ = ({_zz_293_,_zz_294_} != (2'b00)); + assign _zz_289_ = {(_zz_295_ != _zz_296_),{_zz_297_,{_zz_298_,_zz_299_}}}; + assign _zz_290_ = (32'b00010000000000000011000001010000); + assign _zz_291_ = ((decode_INSTRUCTION & (32'b00010000000100000011000001010000)) == (32'b00000000000100000000000001010000)); + assign _zz_292_ = ((decode_INSTRUCTION & (32'b00010000010000000011000001010000)) == (32'b00010000000000000000000001010000)); + assign _zz_293_ = ((decode_INSTRUCTION & _zz_300_) == (32'b00000000000000000110000000010000)); + assign _zz_294_ = ((decode_INSTRUCTION & _zz_301_) == (32'b00000000000000000100000000010000)); + assign _zz_295_ = ((decode_INSTRUCTION & _zz_302_) == (32'b00000000000000000010000000010000)); + assign _zz_296_ = (1'b0); + assign _zz_297_ = ((_zz_303_ == _zz_304_) != (1'b0)); + assign _zz_298_ = ({_zz_305_,_zz_306_} != (2'b00)); + assign _zz_299_ = {(_zz_307_ != _zz_308_),{_zz_309_,{_zz_310_,_zz_311_}}}; + assign _zz_300_ = (32'b00000000000000000110000000010100); + assign _zz_301_ = (32'b00000000000000000101000000010100); + assign _zz_302_ = (32'b00000000000000000110000000010100); + assign _zz_303_ = (decode_INSTRUCTION & (32'b00000000000000000001000001001000)); + assign _zz_304_ = (32'b00000000000000000001000000001000); + assign _zz_305_ = _zz_88_; + assign _zz_306_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001110000)) == (32'b00000000000000000000000000100000)); + assign _zz_307_ = {_zz_88_,((decode_INSTRUCTION & _zz_312_) == (32'b00000000000000000000000000000000))}; + assign _zz_308_ = (2'b00); + assign _zz_309_ = (((decode_INSTRUCTION & _zz_313_) == (32'b00000000000000000101000000010000)) != (1'b0)); + assign _zz_310_ = ({_zz_314_,_zz_315_} != (2'b00)); + assign _zz_311_ = {(_zz_316_ != (1'b0)),{(_zz_317_ != _zz_318_),(_zz_319_ != _zz_320_)}}; + assign _zz_312_ = (32'b00000000000000000000000000100000); + assign _zz_313_ = (32'b00000000000000000111000001010100); + assign _zz_314_ = ((decode_INSTRUCTION & (32'b01000000000000000011000001010100)) == (32'b01000000000000000001000000010000)); + assign _zz_315_ = ((decode_INSTRUCTION & (32'b00000000000000000111000001010100)) == (32'b00000000000000000001000000010000)); + assign _zz_316_ = ((decode_INSTRUCTION & (32'b00000000000000000000000000010000)) == (32'b00000000000000000000000000010000)); + assign _zz_317_ = ((decode_INSTRUCTION & (32'b00000000000000000000000000000000)) == (32'b00000000000000000000000000000000)); + assign _zz_318_ = (1'b0); + assign _zz_319_ = {((decode_INSTRUCTION & (32'b00000000000000000001000001010000)) == (32'b00000000000000000001000001010000)),((decode_INSTRUCTION & (32'b00000000000000000010000001010000)) == (32'b00000000000000000010000001010000))}; + assign _zz_320_ = (2'b00); + assign _zz_321_ = (32'b00000000000000000001000001111111); + assign _zz_322_ = (decode_INSTRUCTION & (32'b00000000000000000010000001111111)); + assign _zz_323_ = (32'b00000000000000000010000001110011); + assign _zz_324_ = ((decode_INSTRUCTION & (32'b00000000000000000100000001111111)) == (32'b00000000000000000100000001100011)); + assign _zz_325_ = ((decode_INSTRUCTION & (32'b00000000000000000010000001111111)) == (32'b00000000000000000010000000010011)); + assign _zz_326_ = {((decode_INSTRUCTION & (32'b00000000000000000110000000111111)) == (32'b00000000000000000000000000100011)),{((decode_INSTRUCTION & (32'b00000000000000000010000001111111)) == (32'b00000000000000000000000000000011)),{((decode_INSTRUCTION & _zz_327_) == (32'b00000000000000000000000000000011)),{(_zz_328_ == _zz_329_),{_zz_330_,{_zz_331_,_zz_332_}}}}}}; + assign _zz_327_ = (32'b00000000000000000101000001011111); + assign _zz_328_ = (decode_INSTRUCTION & (32'b00000000000000000111000001111011)); + assign _zz_329_ = (32'b00000000000000000000000001100011); + assign _zz_330_ = ((decode_INSTRUCTION & (32'b00000000000000000110000001111111)) == (32'b00000000000000000000000000001111)); + assign _zz_331_ = ((decode_INSTRUCTION & (32'b11111110000000000000000001111111)) == (32'b00000000000000000000000000110011)); + assign _zz_332_ = {((decode_INSTRUCTION & (32'b10111100000000000111000001111111)) == (32'b00000000000000000101000000010011)),{((decode_INSTRUCTION & (32'b11111100000000000011000001111111)) == (32'b00000000000000000001000000010011)),{((decode_INSTRUCTION & _zz_333_) == (32'b00000000000000000101000000110011)),{(_zz_334_ == _zz_335_),{_zz_336_,{_zz_337_,_zz_338_}}}}}}; + assign _zz_333_ = (32'b10111110000000000111000001111111); + assign _zz_334_ = (decode_INSTRUCTION & (32'b10111110000000000111000001111111)); + assign _zz_335_ = (32'b00000000000000000000000000110011); + assign _zz_336_ = ((decode_INSTRUCTION & (32'b11011111111111111111111111111111)) == (32'b00010000001000000000000001110011)); + assign _zz_337_ = ((decode_INSTRUCTION & (32'b11111111111011111111111111111111)) == (32'b00000000000000000000000001110011)); + assign _zz_338_ = ((decode_INSTRUCTION & (32'b11111111111111111111111111111111)) == (32'b00010000010100000000000001110011)); + initial begin + $readmemb("2-stage-1024-cache.v_toplevel_RegFilePlugin_regFile.bin",RegFilePlugin_regFile); + end + always @ (posedge clk) begin + if(_zz_40_) begin + RegFilePlugin_regFile[execute_RegFilePlugin_regFileWrite_payload_address] <= execute_RegFilePlugin_regFileWrite_payload_data; + end + end + + always @ (posedge clk) begin + if(_zz_99_) begin + _zz_148_ <= RegFilePlugin_regFile[execute_RegFilePlugin_regFileReadAddress1]; + end + end + + always @ (posedge clk) begin + if(_zz_99_) begin + _zz_149_ <= RegFilePlugin_regFile[execute_RegFilePlugin_regFileReadAddress2]; + end + end + + InstructionCache IBusCachedPlugin_cache ( + .io_flush(_zz_130_), + .io_cpu_prefetch_isValid(_zz_131_), + .io_cpu_prefetch_haltIt(IBusCachedPlugin_cache_io_cpu_prefetch_haltIt), + .io_cpu_prefetch_pc(IBusCachedPlugin_iBusRsp_stages_0_input_payload), + .io_cpu_fetch_isValid(_zz_132_), + .io_cpu_fetch_isStuck(_zz_133_), + .io_cpu_fetch_isRemoved(_zz_134_), + .io_cpu_fetch_pc(IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload), + .io_cpu_fetch_data(IBusCachedPlugin_cache_io_cpu_fetch_data), + .io_cpu_fetch_dataBypassValid(IBusCachedPlugin_s1_tightlyCoupledHit), + .io_cpu_fetch_dataBypass(_zz_135_), + .io_cpu_fetch_mmuBus_cmd_isValid(IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_isValid), + .io_cpu_fetch_mmuBus_cmd_virtualAddress(IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_virtualAddress), + .io_cpu_fetch_mmuBus_cmd_bypassTranslation(IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_bypassTranslation), + .io_cpu_fetch_mmuBus_rsp_physicalAddress(IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_virtualAddress), + .io_cpu_fetch_mmuBus_rsp_isIoAccess(_zz_136_), + .io_cpu_fetch_mmuBus_rsp_allowRead(_zz_137_), + .io_cpu_fetch_mmuBus_rsp_allowWrite(_zz_138_), + .io_cpu_fetch_mmuBus_rsp_allowExecute(_zz_139_), + .io_cpu_fetch_mmuBus_rsp_exception(_zz_140_), + .io_cpu_fetch_mmuBus_rsp_refilling(_zz_141_), + .io_cpu_fetch_mmuBus_end(IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_end), + .io_cpu_fetch_mmuBus_busy(_zz_142_), + .io_cpu_fetch_physicalAddress(IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress), + .io_cpu_fetch_cacheMiss(IBusCachedPlugin_cache_io_cpu_fetch_cacheMiss), + .io_cpu_fetch_error(IBusCachedPlugin_cache_io_cpu_fetch_error), + .io_cpu_fetch_mmuRefilling(IBusCachedPlugin_cache_io_cpu_fetch_mmuRefilling), + .io_cpu_fetch_mmuException(IBusCachedPlugin_cache_io_cpu_fetch_mmuException), + .io_cpu_fetch_isUser(_zz_143_), + .io_cpu_fetch_haltIt(IBusCachedPlugin_cache_io_cpu_fetch_haltIt), + .io_cpu_decode_isValid(_zz_144_), + .io_cpu_decode_isStuck(_zz_145_), + .io_cpu_decode_pc(_zz_146_), + .io_cpu_decode_physicalAddress(IBusCachedPlugin_cache_io_cpu_decode_physicalAddress), + .io_cpu_decode_data(IBusCachedPlugin_cache_io_cpu_decode_data), + .io_cpu_fill_valid(_zz_147_), + .io_cpu_fill_payload(IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress), + .io_mem_cmd_valid(IBusCachedPlugin_cache_io_mem_cmd_valid), + .io_mem_cmd_ready(iBus_cmd_ready), + .io_mem_cmd_payload_address(IBusCachedPlugin_cache_io_mem_cmd_payload_address), + .io_mem_cmd_payload_size(IBusCachedPlugin_cache_io_mem_cmd_payload_size), + .io_mem_rsp_valid(iBus_rsp_valid), + .io_mem_rsp_payload_data(iBus_rsp_payload_data), + .io_mem_rsp_payload_error(iBus_rsp_payload_error), + .clk(clk), + .reset(reset) + ); + always @(*) begin + case(_zz_205_) + 2'b00 : begin + _zz_150_ = BranchPlugin_jumpInterface_payload; + end + 2'b01 : begin + _zz_150_ = CsrPlugin_jumpInterface_payload; + end + default : begin + _zz_150_ = IBusCachedPlugin_redoBranch_payload; + end + endcase + end + + always @(*) begin + case(_zz_124_) + 2'b00 : begin + _zz_151_ = DBusSimplePlugin_memoryExceptionPort_payload_code; + _zz_152_ = DBusSimplePlugin_memoryExceptionPort_payload_badAddr; + end + 2'b01 : begin + _zz_151_ = BranchPlugin_branchExceptionPort_payload_code; + _zz_152_ = BranchPlugin_branchExceptionPort_payload_badAddr; + end + default : begin + _zz_151_ = CsrPlugin_selfException_payload_code; + _zz_152_ = CsrPlugin_selfException_payload_badAddr; + end + endcase + end + + `ifndef SYNTHESIS + always @(*) begin + case(decode_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : decode_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : decode_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : decode_ENV_CTRL_string = "ECALL "; + `EnvCtrlEnum_defaultEncoding_EBREAK : decode_ENV_CTRL_string = "EBREAK"; + default : decode_ENV_CTRL_string = "??????"; + endcase + end + always @(*) begin + case(_zz_1_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_1__string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_1__string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_1__string = "ECALL "; + `EnvCtrlEnum_defaultEncoding_EBREAK : _zz_1__string = "EBREAK"; + default : _zz_1__string = "??????"; + endcase + end + always @(*) begin + case(_zz_2_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_2__string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_2__string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_2__string = "ECALL "; + `EnvCtrlEnum_defaultEncoding_EBREAK : _zz_2__string = "EBREAK"; + default : _zz_2__string = "??????"; + endcase + end + always @(*) begin + case(_zz_3_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_3__string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_3__string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_3__string = "ECALL "; + `EnvCtrlEnum_defaultEncoding_EBREAK : _zz_3__string = "EBREAK"; + default : _zz_3__string = "??????"; + endcase + end + always @(*) begin + case(decode_SRC2_CTRL) + `Src2CtrlEnum_defaultEncoding_RS : decode_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : decode_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : decode_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : decode_SRC2_CTRL_string = "PC "; + default : decode_SRC2_CTRL_string = "???"; + endcase + end + always @(*) begin + case(_zz_4_) + `Src2CtrlEnum_defaultEncoding_RS : _zz_4__string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_4__string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_4__string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_4__string = "PC "; + default : _zz_4__string = "???"; + endcase + end + always @(*) begin + case(_zz_5_) + `Src2CtrlEnum_defaultEncoding_RS : _zz_5__string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_5__string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_5__string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_5__string = "PC "; + default : _zz_5__string = "???"; + endcase + end + always @(*) begin + case(_zz_6_) + `Src2CtrlEnum_defaultEncoding_RS : _zz_6__string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_6__string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_6__string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_6__string = "PC "; + default : _zz_6__string = "???"; + endcase + end + always @(*) begin + case(decode_SRC1_CTRL) + `Src1CtrlEnum_defaultEncoding_RS : decode_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : decode_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : decode_SRC1_CTRL_string = "URS1 "; + default : decode_SRC1_CTRL_string = "????????????"; + endcase + end + always @(*) begin + case(_zz_7_) + `Src1CtrlEnum_defaultEncoding_RS : _zz_7__string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_7__string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_7__string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_7__string = "URS1 "; + default : _zz_7__string = "????????????"; + endcase + end + always @(*) begin + case(_zz_8_) + `Src1CtrlEnum_defaultEncoding_RS : _zz_8__string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_8__string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_8__string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_8__string = "URS1 "; + default : _zz_8__string = "????????????"; + endcase + end + always @(*) begin + case(_zz_9_) + `Src1CtrlEnum_defaultEncoding_RS : _zz_9__string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_9__string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_9__string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_9__string = "URS1 "; + default : _zz_9__string = "????????????"; + endcase + end + always @(*) begin + case(decode_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : decode_ALU_CTRL_string = "BITWISE "; + default : decode_ALU_CTRL_string = "????????"; + endcase + end + always @(*) begin + case(_zz_10_) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_10__string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_10__string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_10__string = "BITWISE "; + default : _zz_10__string = "????????"; + endcase + end + always @(*) begin + case(_zz_11_) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_11__string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_11__string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_11__string = "BITWISE "; + default : _zz_11__string = "????????"; + endcase + end + always @(*) begin + case(_zz_12_) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_12__string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_12__string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_12__string = "BITWISE "; + default : _zz_12__string = "????????"; + endcase + end + always @(*) begin + case(decode_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : decode_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : decode_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : decode_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : decode_BRANCH_CTRL_string = "JALR"; + default : decode_BRANCH_CTRL_string = "????"; + endcase + end + always @(*) begin + case(_zz_13_) + `BranchCtrlEnum_defaultEncoding_INC : _zz_13__string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_13__string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_13__string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_13__string = "JALR"; + default : _zz_13__string = "????"; + endcase + end + always @(*) begin + case(_zz_14_) + `BranchCtrlEnum_defaultEncoding_INC : _zz_14__string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_14__string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_14__string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_14__string = "JALR"; + default : _zz_14__string = "????"; + endcase + end + always @(*) begin + case(_zz_15_) + `BranchCtrlEnum_defaultEncoding_INC : _zz_15__string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_15__string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_15__string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_15__string = "JALR"; + default : _zz_15__string = "????"; + endcase + end + always @(*) begin + case(decode_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_SHIFT_CTRL_string = "SRA_1 "; + default : decode_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_16_) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_16__string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_16__string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_16__string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_16__string = "SRA_1 "; + default : _zz_16__string = "?????????"; + endcase + end + always @(*) begin + case(_zz_17_) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_17__string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_17__string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_17__string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_17__string = "SRA_1 "; + default : _zz_17__string = "?????????"; + endcase + end + always @(*) begin + case(_zz_18_) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_18__string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_18__string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_18__string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_18__string = "SRA_1 "; + default : _zz_18__string = "?????????"; + endcase + end + always @(*) begin + case(decode_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_ALU_BITWISE_CTRL_string = "AND_1"; + default : decode_ALU_BITWISE_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_19_) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_19__string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_19__string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_19__string = "AND_1"; + default : _zz_19__string = "?????"; + endcase + end + always @(*) begin + case(_zz_20_) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_20__string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_20__string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_20__string = "AND_1"; + default : _zz_20__string = "?????"; + endcase + end + always @(*) begin + case(_zz_21_) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_21__string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_21__string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_21__string = "AND_1"; + default : _zz_21__string = "?????"; + endcase + end + always @(*) begin + case(execute_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : execute_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : execute_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : execute_ENV_CTRL_string = "ECALL "; + `EnvCtrlEnum_defaultEncoding_EBREAK : execute_ENV_CTRL_string = "EBREAK"; + default : execute_ENV_CTRL_string = "??????"; + endcase + end + always @(*) begin + case(_zz_24_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_24__string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_24__string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_24__string = "ECALL "; + `EnvCtrlEnum_defaultEncoding_EBREAK : _zz_24__string = "EBREAK"; + default : _zz_24__string = "??????"; + endcase + end + always @(*) begin + case(execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : execute_BRANCH_CTRL_string = "JALR"; + default : execute_BRANCH_CTRL_string = "????"; + endcase + end + always @(*) begin + case(_zz_26_) + `BranchCtrlEnum_defaultEncoding_INC : _zz_26__string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_26__string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_26__string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_26__string = "JALR"; + default : _zz_26__string = "????"; + endcase + end + always @(*) begin + case(execute_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : execute_SHIFT_CTRL_string = "SRA_1 "; + default : execute_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(_zz_28_) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_28__string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_28__string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_28__string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_28__string = "SRA_1 "; + default : _zz_28__string = "?????????"; + endcase + end + always @(*) begin + case(execute_SRC2_CTRL) + `Src2CtrlEnum_defaultEncoding_RS : execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : execute_SRC2_CTRL_string = "PC "; + default : execute_SRC2_CTRL_string = "???"; + endcase + end + always @(*) begin + case(_zz_32_) + `Src2CtrlEnum_defaultEncoding_RS : _zz_32__string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_32__string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_32__string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_32__string = "PC "; + default : _zz_32__string = "???"; + endcase + end + always @(*) begin + case(execute_SRC1_CTRL) + `Src1CtrlEnum_defaultEncoding_RS : execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : execute_SRC1_CTRL_string = "URS1 "; + default : execute_SRC1_CTRL_string = "????????????"; + endcase + end + always @(*) begin + case(_zz_34_) + `Src1CtrlEnum_defaultEncoding_RS : _zz_34__string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_34__string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_34__string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_34__string = "URS1 "; + default : _zz_34__string = "????????????"; + endcase + end + always @(*) begin + case(execute_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_ADD_SUB : execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : execute_ALU_CTRL_string = "BITWISE "; + default : execute_ALU_CTRL_string = "????????"; + endcase + end + always @(*) begin + case(_zz_37_) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_37__string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_37__string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_37__string = "BITWISE "; + default : _zz_37__string = "????????"; + endcase + end + always @(*) begin + case(execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : execute_ALU_BITWISE_CTRL_string = "AND_1"; + default : execute_ALU_BITWISE_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(_zz_39_) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_39__string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_39__string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_39__string = "AND_1"; + default : _zz_39__string = "?????"; + endcase + end + always @(*) begin + case(_zz_45_) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_45__string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_45__string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_45__string = "AND_1"; + default : _zz_45__string = "?????"; + endcase + end + always @(*) begin + case(_zz_50_) + `Src1CtrlEnum_defaultEncoding_RS : _zz_50__string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_50__string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_50__string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_50__string = "URS1 "; + default : _zz_50__string = "????????????"; + endcase + end + always @(*) begin + case(_zz_51_) + `BranchCtrlEnum_defaultEncoding_INC : _zz_51__string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_51__string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_51__string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_51__string = "JALR"; + default : _zz_51__string = "????"; + endcase + end + always @(*) begin + case(_zz_52_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_52__string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_52__string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_52__string = "ECALL "; + `EnvCtrlEnum_defaultEncoding_EBREAK : _zz_52__string = "EBREAK"; + default : _zz_52__string = "??????"; + endcase + end + always @(*) begin + case(_zz_53_) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_53__string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_53__string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_53__string = "BITWISE "; + default : _zz_53__string = "????????"; + endcase + end + always @(*) begin + case(_zz_55_) + `Src2CtrlEnum_defaultEncoding_RS : _zz_55__string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_55__string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_55__string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_55__string = "PC "; + default : _zz_55__string = "???"; + endcase + end + always @(*) begin + case(_zz_56_) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_56__string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_56__string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_56__string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_56__string = "SRA_1 "; + default : _zz_56__string = "?????????"; + endcase + end + always @(*) begin + case(_zz_92_) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : _zz_92__string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : _zz_92__string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : _zz_92__string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : _zz_92__string = "SRA_1 "; + default : _zz_92__string = "?????????"; + endcase + end + always @(*) begin + case(_zz_93_) + `Src2CtrlEnum_defaultEncoding_RS : _zz_93__string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : _zz_93__string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : _zz_93__string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : _zz_93__string = "PC "; + default : _zz_93__string = "???"; + endcase + end + always @(*) begin + case(_zz_94_) + `AluCtrlEnum_defaultEncoding_ADD_SUB : _zz_94__string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : _zz_94__string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : _zz_94__string = "BITWISE "; + default : _zz_94__string = "????????"; + endcase + end + always @(*) begin + case(_zz_95_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_95__string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : _zz_95__string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : _zz_95__string = "ECALL "; + `EnvCtrlEnum_defaultEncoding_EBREAK : _zz_95__string = "EBREAK"; + default : _zz_95__string = "??????"; + endcase + end + always @(*) begin + case(_zz_96_) + `BranchCtrlEnum_defaultEncoding_INC : _zz_96__string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : _zz_96__string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : _zz_96__string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : _zz_96__string = "JALR"; + default : _zz_96__string = "????"; + endcase + end + always @(*) begin + case(_zz_97_) + `Src1CtrlEnum_defaultEncoding_RS : _zz_97__string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : _zz_97__string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : _zz_97__string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : _zz_97__string = "URS1 "; + default : _zz_97__string = "????????????"; + endcase + end + always @(*) begin + case(_zz_98_) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_98__string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_98__string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_98__string = "AND_1"; + default : _zz_98__string = "?????"; + endcase + end + always @(*) begin + case(decode_to_execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "XOR_1"; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_to_execute_ALU_BITWISE_CTRL_string = "AND_1"; + default : decode_to_execute_ALU_BITWISE_CTRL_string = "?????"; + endcase + end + always @(*) begin + case(decode_to_execute_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_DISABLE_1 : decode_to_execute_SHIFT_CTRL_string = "DISABLE_1"; + `ShiftCtrlEnum_defaultEncoding_SLL_1 : decode_to_execute_SHIFT_CTRL_string = "SLL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRL_1 : decode_to_execute_SHIFT_CTRL_string = "SRL_1 "; + `ShiftCtrlEnum_defaultEncoding_SRA_1 : decode_to_execute_SHIFT_CTRL_string = "SRA_1 "; + default : decode_to_execute_SHIFT_CTRL_string = "?????????"; + endcase + end + always @(*) begin + case(decode_to_execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : decode_to_execute_BRANCH_CTRL_string = "INC "; + `BranchCtrlEnum_defaultEncoding_B : decode_to_execute_BRANCH_CTRL_string = "B "; + `BranchCtrlEnum_defaultEncoding_JAL : decode_to_execute_BRANCH_CTRL_string = "JAL "; + `BranchCtrlEnum_defaultEncoding_JALR : decode_to_execute_BRANCH_CTRL_string = "JALR"; + default : decode_to_execute_BRANCH_CTRL_string = "????"; + endcase + end + always @(*) begin + case(decode_to_execute_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_ADD_SUB : decode_to_execute_ALU_CTRL_string = "ADD_SUB "; + `AluCtrlEnum_defaultEncoding_SLT_SLTU : decode_to_execute_ALU_CTRL_string = "SLT_SLTU"; + `AluCtrlEnum_defaultEncoding_BITWISE : decode_to_execute_ALU_CTRL_string = "BITWISE "; + default : decode_to_execute_ALU_CTRL_string = "????????"; + endcase + end + always @(*) begin + case(decode_to_execute_SRC1_CTRL) + `Src1CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC1_CTRL_string = "RS "; + `Src1CtrlEnum_defaultEncoding_IMU : decode_to_execute_SRC1_CTRL_string = "IMU "; + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : decode_to_execute_SRC1_CTRL_string = "PC_INCREMENT"; + `Src1CtrlEnum_defaultEncoding_URS1 : decode_to_execute_SRC1_CTRL_string = "URS1 "; + default : decode_to_execute_SRC1_CTRL_string = "????????????"; + endcase + end + always @(*) begin + case(decode_to_execute_SRC2_CTRL) + `Src2CtrlEnum_defaultEncoding_RS : decode_to_execute_SRC2_CTRL_string = "RS "; + `Src2CtrlEnum_defaultEncoding_IMI : decode_to_execute_SRC2_CTRL_string = "IMI"; + `Src2CtrlEnum_defaultEncoding_IMS : decode_to_execute_SRC2_CTRL_string = "IMS"; + `Src2CtrlEnum_defaultEncoding_PC : decode_to_execute_SRC2_CTRL_string = "PC "; + default : decode_to_execute_SRC2_CTRL_string = "???"; + endcase + end + always @(*) begin + case(decode_to_execute_ENV_CTRL) + `EnvCtrlEnum_defaultEncoding_NONE : decode_to_execute_ENV_CTRL_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_XRET : decode_to_execute_ENV_CTRL_string = "XRET "; + `EnvCtrlEnum_defaultEncoding_ECALL : decode_to_execute_ENV_CTRL_string = "ECALL "; + `EnvCtrlEnum_defaultEncoding_EBREAK : decode_to_execute_ENV_CTRL_string = "EBREAK"; + default : decode_to_execute_ENV_CTRL_string = "??????"; + endcase + end + `endif + + assign decode_CSR_WRITE_OPCODE = _zz_23_; + assign decode_SRC_LESS_UNSIGNED = _zz_47_; + assign decode_ENV_CTRL = _zz_1_; + assign _zz_2_ = _zz_3_; + assign execute_FORMAL_PC_NEXT = decode_to_execute_FORMAL_PC_NEXT; + assign decode_FORMAL_PC_NEXT = _zz_67_; + assign decode_SRC2_CTRL = _zz_4_; + assign _zz_5_ = _zz_6_; + assign decode_IS_CSR = _zz_57_; + assign decode_MEMORY_ENABLE = _zz_49_; + assign decode_SRC1_CTRL = _zz_7_; + assign _zz_8_ = _zz_9_; + assign decode_CSR_READ_OPCODE = _zz_22_; + assign execute_REGFILE_WRITE_VALID = decode_to_execute_REGFILE_WRITE_VALID; + assign decode_ALU_CTRL = _zz_10_; + assign _zz_11_ = _zz_12_; + assign decode_SRC2_FORCE_ZERO = _zz_36_; + assign decode_MEMORY_STORE = _zz_48_; + assign decode_BRANCH_CTRL = _zz_13_; + assign _zz_14_ = _zz_15_; + assign decode_SHIFT_CTRL = _zz_16_; + assign _zz_17_ = _zz_18_; + assign decode_ALU_BITWISE_CTRL = _zz_19_; + assign _zz_20_ = _zz_21_; + assign execute_CSR_READ_OPCODE = decode_to_execute_CSR_READ_OPCODE; + assign execute_CSR_WRITE_OPCODE = decode_to_execute_CSR_WRITE_OPCODE; + assign execute_IS_CSR = decode_to_execute_IS_CSR; + assign execute_ENV_CTRL = _zz_24_; + assign execute_BRANCH_CALC = _zz_25_; + assign execute_BRANCH_DO = _zz_27_; + assign execute_PC = decode_to_execute_PC; + assign execute_RS1 = _zz_42_; + assign execute_BRANCH_CTRL = _zz_26_; + assign execute_SHIFT_CTRL = _zz_28_; + assign execute_SRC_LESS_UNSIGNED = decode_to_execute_SRC_LESS_UNSIGNED; + assign execute_SRC2_FORCE_ZERO = decode_to_execute_SRC2_FORCE_ZERO; + assign execute_SRC_USE_SUB_LESS = decode_to_execute_SRC_USE_SUB_LESS; + assign execute_SRC2_CTRL = _zz_32_; + assign execute_SRC1_CTRL = _zz_34_; + assign decode_SRC_USE_SUB_LESS = _zz_46_; + assign decode_SRC_ADD_ZERO = _zz_43_; + assign execute_SRC_ADD_SUB = _zz_31_; + assign execute_SRC_LESS = _zz_29_; + assign execute_ALU_CTRL = _zz_37_; + assign execute_SRC2 = _zz_33_; + assign execute_SRC1 = _zz_35_; + assign execute_ALU_BITWISE_CTRL = _zz_39_; + always @ (*) begin + _zz_40_ = 1'b0; + if(execute_RegFilePlugin_regFileWrite_valid)begin + _zz_40_ = 1'b1; + end + end + + always @ (*) begin + decode_REGFILE_WRITE_VALID = _zz_44_; + if((decode_INSTRUCTION[11 : 7] == (5'b00000)))begin + decode_REGFILE_WRITE_VALID = 1'b0; + end + end + + assign decode_LEGAL_INSTRUCTION = _zz_58_; + assign decode_INSTRUCTION_READY = 1'b1; + always @ (*) begin + _zz_59_ = execute_REGFILE_WRITE_DATA; + execute_arbitration_haltItself = 1'b0; + if(((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! dBus_cmd_ready)) && (! execute_DBusSimplePlugin_skipCmd)) && (! execute_DBusSimplePlugin_cmdSent)))begin + execute_arbitration_haltItself = 1'b1; + end + if((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! execute_MEMORY_STORE)) && (! dBus_rsp_ready)))begin + execute_arbitration_haltItself = 1'b1; + end + if((execute_arbitration_isValid && execute_MEMORY_ENABLE))begin + _zz_59_ = execute_DBusSimplePlugin_rspFormated; + end + if(_zz_153_)begin + _zz_59_ = _zz_107_; + if(_zz_154_)begin + if(! execute_LightShifterPlugin_done) begin + execute_arbitration_haltItself = 1'b1; + end + end + end + if((execute_arbitration_isValid && execute_IS_CSR))begin + _zz_59_ = execute_CsrPlugin_readData; + if(execute_CsrPlugin_blockedBySideEffects)begin + execute_arbitration_haltItself = 1'b1; + end + end + end + + assign execute_MEMORY_ADDRESS_LOW = _zz_61_; + assign execute_MEMORY_READ_DATA = _zz_60_; + assign execute_REGFILE_WRITE_DATA = _zz_38_; + assign execute_SRC_ADD = _zz_30_; + assign execute_RS2 = _zz_41_; + assign execute_INSTRUCTION = decode_to_execute_INSTRUCTION; + assign execute_MEMORY_STORE = decode_to_execute_MEMORY_STORE; + assign execute_MEMORY_ENABLE = decode_to_execute_MEMORY_ENABLE; + assign execute_ALIGNEMENT_FAULT = _zz_62_; + assign decode_FLUSH_ALL = _zz_54_; + always @ (*) begin + IBusCachedPlugin_rsp_issueDetected = _zz_63_; + _zz_64_ = _zz_65_; + IBusCachedPlugin_decodeExceptionPort_valid = 1'b0; + IBusCachedPlugin_decodeExceptionPort_payload_code = (4'bxxxx); + if(((_zz_132_ && IBusCachedPlugin_cache_io_cpu_fetch_mmuException) && (! _zz_65_)))begin + _zz_64_ = 1'b1; + IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; + IBusCachedPlugin_decodeExceptionPort_payload_code = (4'b1100); + end + if(((_zz_132_ && IBusCachedPlugin_cache_io_cpu_fetch_error) && (! _zz_63_)))begin + IBusCachedPlugin_rsp_issueDetected = 1'b1; + IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; + IBusCachedPlugin_decodeExceptionPort_payload_code = (4'b0001); + end + if(IBusCachedPlugin_fetcherHalt)begin + IBusCachedPlugin_decodeExceptionPort_valid = 1'b0; + end + end + + always @ (*) begin + _zz_63_ = _zz_64_; + _zz_65_ = 1'b0; + IBusCachedPlugin_rsp_redoFetch = 1'b0; + _zz_147_ = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_fetch_mmuRefilling)); + if(((_zz_132_ && IBusCachedPlugin_cache_io_cpu_fetch_mmuRefilling) && (! 1'b0)))begin + _zz_65_ = 1'b1; + IBusCachedPlugin_rsp_redoFetch = 1'b1; + end + if(((_zz_132_ && IBusCachedPlugin_cache_io_cpu_fetch_cacheMiss) && (! _zz_64_)))begin + _zz_63_ = 1'b1; + _zz_147_ = 1'b1; + IBusCachedPlugin_rsp_redoFetch = 1'b1; + end + if((! IBusCachedPlugin_iBusRsp_readyForError))begin + IBusCachedPlugin_rsp_redoFetch = 1'b0; + end + if((! IBusCachedPlugin_iBusRsp_readyForError))begin + _zz_147_ = 1'b0; + end + end + + always @ (*) begin + _zz_66_ = decode_FORMAL_PC_NEXT; + if(IBusCachedPlugin_redoBranch_valid)begin + _zz_66_ = IBusCachedPlugin_redoBranch_payload; + end + end + + assign decode_PC = _zz_69_; + assign decode_INSTRUCTION = _zz_68_; + assign decode_arbitration_haltItself = 1'b0; + always @ (*) begin + decode_arbitration_haltByOther = 1'b0; + if(CsrPlugin_interrupt)begin + decode_arbitration_haltByOther = decode_arbitration_isValid; + end + if(((execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)) != (1'b0)))begin + decode_arbitration_haltByOther = 1'b1; + end + end + + always @ (*) begin + decode_arbitration_removeIt = 1'b0; + if(_zz_155_)begin + decode_arbitration_removeIt = 1'b1; + end + if(decode_arbitration_isFlushed)begin + decode_arbitration_removeIt = 1'b1; + end + end + + always @ (*) begin + decode_arbitration_flushAll = 1'b0; + execute_arbitration_removeIt = 1'b0; + IBusCachedPlugin_fetcherHalt = 1'b0; + CsrPlugin_jumpInterface_valid = 1'b0; + CsrPlugin_jumpInterface_payload = (32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx); + if(BranchPlugin_jumpInterface_valid)begin + decode_arbitration_flushAll = 1'b1; + end + CsrPlugin_exceptionPortCtrl_exceptionValids_execute = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; + if(_zz_156_)begin + decode_arbitration_flushAll = 1'b1; + execute_arbitration_removeIt = 1'b1; + CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b1; + end + if(execute_arbitration_isFlushed)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b0; + end + if(({CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute,CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode} != (2'b00)))begin + IBusCachedPlugin_fetcherHalt = 1'b1; + end + if(_zz_157_)begin + IBusCachedPlugin_fetcherHalt = 1'b1; + CsrPlugin_jumpInterface_valid = 1'b1; + CsrPlugin_jumpInterface_payload = {CsrPlugin_xtvec_base,(2'b00)}; + decode_arbitration_flushAll = 1'b1; + end + if(_zz_158_)begin + IBusCachedPlugin_fetcherHalt = 1'b1; + CsrPlugin_jumpInterface_valid = 1'b1; + decode_arbitration_flushAll = 1'b1; + case(_zz_159_) + 2'b11 : begin + CsrPlugin_jumpInterface_payload = CsrPlugin_mepc; + end + default : begin + end + endcase + end + if(execute_arbitration_isFlushed)begin + execute_arbitration_removeIt = 1'b1; + end + end + + assign execute_arbitration_haltByOther = 1'b0; + assign execute_arbitration_flushAll = 1'b0; + assign IBusCachedPlugin_fetcherflushIt = 1'b0; + always @ (*) begin + IBusCachedPlugin_incomingInstruction = 1'b0; + if(IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid)begin + IBusCachedPlugin_incomingInstruction = 1'b1; + end + end + + assign CsrPlugin_forceMachineWire = 1'b0; + assign CsrPlugin_allowInterrupts = 1'b1; + assign CsrPlugin_allowException = 1'b1; + assign IBusCachedPlugin_jump_pcLoad_valid = ({CsrPlugin_jumpInterface_valid,{BranchPlugin_jumpInterface_valid,IBusCachedPlugin_redoBranch_valid}} != (3'b000)); + assign _zz_70_ = {IBusCachedPlugin_redoBranch_valid,{CsrPlugin_jumpInterface_valid,BranchPlugin_jumpInterface_valid}}; + assign _zz_71_ = (_zz_70_ & (~ _zz_165_)); + assign _zz_72_ = _zz_71_[1]; + assign _zz_73_ = _zz_71_[2]; + assign IBusCachedPlugin_jump_pcLoad_payload = _zz_150_; + assign _zz_74_ = (! IBusCachedPlugin_fetcherHalt); + assign IBusCachedPlugin_fetchPc_output_valid = (IBusCachedPlugin_fetchPc_preOutput_valid && _zz_74_); + assign IBusCachedPlugin_fetchPc_preOutput_ready = (IBusCachedPlugin_fetchPc_output_ready && _zz_74_); + assign IBusCachedPlugin_fetchPc_output_payload = IBusCachedPlugin_fetchPc_preOutput_payload; + always @ (*) begin + IBusCachedPlugin_fetchPc_propagatePc = 1'b0; + if((IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid && IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready))begin + IBusCachedPlugin_fetchPc_propagatePc = 1'b1; + end + end + + always @ (*) begin + IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_167_); + IBusCachedPlugin_fetchPc_samplePcNext = 1'b0; + if(IBusCachedPlugin_fetchPc_propagatePc)begin + IBusCachedPlugin_fetchPc_samplePcNext = 1'b1; + end + if(IBusCachedPlugin_jump_pcLoad_valid)begin + IBusCachedPlugin_fetchPc_samplePcNext = 1'b1; + IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_jump_pcLoad_payload; + end + if(_zz_160_)begin + IBusCachedPlugin_fetchPc_samplePcNext = 1'b1; + end + IBusCachedPlugin_fetchPc_pc[0] = 1'b0; + IBusCachedPlugin_fetchPc_pc[1] = 1'b0; + end + + assign IBusCachedPlugin_fetchPc_preOutput_valid = _zz_75_; + assign IBusCachedPlugin_fetchPc_preOutput_payload = IBusCachedPlugin_fetchPc_pc; + assign IBusCachedPlugin_iBusRsp_stages_0_input_valid = IBusCachedPlugin_fetchPc_output_valid; + assign IBusCachedPlugin_fetchPc_output_ready = IBusCachedPlugin_iBusRsp_stages_0_input_ready; + assign IBusCachedPlugin_iBusRsp_stages_0_input_payload = IBusCachedPlugin_fetchPc_output_payload; + assign IBusCachedPlugin_iBusRsp_stages_0_inputSample = 1'b1; + always @ (*) begin + IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b0; + if(IBusCachedPlugin_cache_io_cpu_prefetch_haltIt)begin + IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b1; + end + end + + assign _zz_76_ = (! IBusCachedPlugin_iBusRsp_stages_0_halt); + assign IBusCachedPlugin_iBusRsp_stages_0_input_ready = (IBusCachedPlugin_iBusRsp_stages_0_output_ready && _zz_76_); + assign IBusCachedPlugin_iBusRsp_stages_0_output_valid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && _zz_76_); + assign IBusCachedPlugin_iBusRsp_stages_0_output_payload = IBusCachedPlugin_iBusRsp_stages_0_input_payload; + always @ (*) begin + IBusCachedPlugin_iBusRsp_cacheRspArbitration_halt = 1'b0; + if(IBusCachedPlugin_cache_io_cpu_fetch_haltIt)begin + IBusCachedPlugin_iBusRsp_cacheRspArbitration_halt = 1'b1; + end + if((IBusCachedPlugin_rsp_issueDetected || IBusCachedPlugin_rsp_iBusRspOutputHalt))begin + IBusCachedPlugin_iBusRsp_cacheRspArbitration_halt = 1'b1; + end + end + + assign _zz_77_ = (! IBusCachedPlugin_iBusRsp_cacheRspArbitration_halt); + assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready = (IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_ready && _zz_77_); + assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_valid = (IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid && _zz_77_); + assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_payload = IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload; + assign IBusCachedPlugin_iBusRsp_stages_0_output_ready = _zz_78_; + assign _zz_78_ = ((1'b0 && (! _zz_79_)) || IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready); + assign _zz_79_ = _zz_80_; + assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid = _zz_79_; + assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload = IBusCachedPlugin_fetchPc_pcReg; + always @ (*) begin + IBusCachedPlugin_iBusRsp_readyForError = 1'b1; + if((! IBusCachedPlugin_pcValids_0))begin + IBusCachedPlugin_iBusRsp_readyForError = 1'b0; + end + end + + assign IBusCachedPlugin_pcValids_0 = IBusCachedPlugin_injector_nextPcCalc_valids_0; + assign IBusCachedPlugin_pcValids_1 = IBusCachedPlugin_injector_nextPcCalc_valids_1; + assign IBusCachedPlugin_iBusRsp_decodeInput_ready = (! decode_arbitration_isStuck); + assign decode_arbitration_isValid = (IBusCachedPlugin_iBusRsp_decodeInput_valid && (! IBusCachedPlugin_injector_decodeRemoved)); + assign _zz_69_ = IBusCachedPlugin_iBusRsp_decodeInput_payload_pc; + assign _zz_68_ = IBusCachedPlugin_iBusRsp_decodeInput_payload_rsp_inst; + assign _zz_67_ = (decode_PC + (32'b00000000000000000000000000000100)); + assign iBus_cmd_valid = IBusCachedPlugin_cache_io_mem_cmd_valid; + always @ (*) begin + iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; + iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; + end + + assign iBus_cmd_payload_size = IBusCachedPlugin_cache_io_mem_cmd_payload_size; + assign IBusCachedPlugin_s0_tightlyCoupledHit = 1'b0; + assign _zz_131_ = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); + assign _zz_134_ = (IBusCachedPlugin_jump_pcLoad_valid || IBusCachedPlugin_fetcherflushIt); + assign _zz_135_ = (32'b00000000000000000000000000000000); + assign _zz_132_ = (IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); + assign _zz_133_ = (! IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready); + assign _zz_143_ = (CsrPlugin_privilege == (2'b00)); + assign IBusCachedPlugin_rsp_iBusRspOutputHalt = 1'b0; + assign IBusCachedPlugin_decodeExceptionPort_payload_badAddr = {IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload[31 : 2],(2'b00)}; + assign IBusCachedPlugin_redoBranch_valid = IBusCachedPlugin_rsp_redoFetch; + assign IBusCachedPlugin_redoBranch_payload = IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_payload; + assign IBusCachedPlugin_iBusRsp_decodeInput_valid = IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_valid; + assign IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_ready = IBusCachedPlugin_iBusRsp_decodeInput_ready; + assign IBusCachedPlugin_iBusRsp_decodeInput_payload_rsp_inst = IBusCachedPlugin_cache_io_cpu_fetch_data; + assign IBusCachedPlugin_iBusRsp_decodeInput_payload_pc = IBusCachedPlugin_iBusRsp_cacheRspArbitration_output_payload; + assign _zz_139_ = 1'b1; + assign _zz_137_ = 1'b1; + assign _zz_138_ = 1'b1; + assign _zz_136_ = 1'b0; + assign _zz_140_ = 1'b0; + assign _zz_141_ = 1'b0; + assign _zz_142_ = 1'b0; + assign _zz_130_ = (decode_arbitration_isValid && decode_FLUSH_ALL); + assign _zz_62_ = (((dBus_cmd_payload_size == (2'b10)) && (dBus_cmd_payload_address[1 : 0] != (2'b00))) || ((dBus_cmd_payload_size == (2'b01)) && (dBus_cmd_payload_address[0 : 0] != (1'b0)))); + always @ (*) begin + execute_DBusSimplePlugin_skipCmd = 1'b0; + if(execute_ALIGNEMENT_FAULT)begin + execute_DBusSimplePlugin_skipCmd = 1'b1; + end + end + + assign dBus_cmd_valid = (((((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (! execute_arbitration_isStuckByOthers)) && (! execute_arbitration_isFlushed)) && (! execute_DBusSimplePlugin_skipCmd)) && (! execute_DBusSimplePlugin_cmdSent)); + assign dBus_cmd_payload_wr = execute_MEMORY_STORE; + assign dBus_cmd_payload_size = execute_INSTRUCTION[13 : 12]; + always @ (*) begin + case(dBus_cmd_payload_size) + 2'b00 : begin + _zz_81_ = {{{execute_RS2[7 : 0],execute_RS2[7 : 0]},execute_RS2[7 : 0]},execute_RS2[7 : 0]}; + end + 2'b01 : begin + _zz_81_ = {execute_RS2[15 : 0],execute_RS2[15 : 0]}; + end + default : begin + _zz_81_ = execute_RS2[31 : 0]; + end + endcase + end + + assign dBus_cmd_payload_data = _zz_81_; + assign _zz_61_ = dBus_cmd_payload_address[1 : 0]; + always @ (*) begin + case(dBus_cmd_payload_size) + 2'b00 : begin + _zz_82_ = (4'b0001); + end + 2'b01 : begin + _zz_82_ = (4'b0011); + end + default : begin + _zz_82_ = (4'b1111); + end + endcase + end + + assign execute_DBusSimplePlugin_formalMask = (_zz_82_ <<< dBus_cmd_payload_address[1 : 0]); + assign dBus_cmd_payload_address = execute_SRC_ADD; + assign _zz_60_ = dBus_rsp_data; + always @ (*) begin + DBusSimplePlugin_memoryExceptionPort_valid = 1'b0; + DBusSimplePlugin_memoryExceptionPort_payload_code = (4'bxxxx); + if(execute_ALIGNEMENT_FAULT)begin + DBusSimplePlugin_memoryExceptionPort_payload_code = {1'd0, _zz_168_}; + DBusSimplePlugin_memoryExceptionPort_valid = 1'b1; + end + if((! ((execute_arbitration_isValid && execute_MEMORY_ENABLE) && (1'b0 || (! execute_arbitration_isStuckByOthers)))))begin + DBusSimplePlugin_memoryExceptionPort_valid = 1'b0; + end + end + + assign DBusSimplePlugin_memoryExceptionPort_payload_badAddr = execute_REGFILE_WRITE_DATA; + always @ (*) begin + execute_DBusSimplePlugin_rspShifted = execute_MEMORY_READ_DATA; + case(execute_MEMORY_ADDRESS_LOW) + 2'b01 : begin + execute_DBusSimplePlugin_rspShifted[7 : 0] = execute_MEMORY_READ_DATA[15 : 8]; + end + 2'b10 : begin + execute_DBusSimplePlugin_rspShifted[15 : 0] = execute_MEMORY_READ_DATA[31 : 16]; + end + 2'b11 : begin + execute_DBusSimplePlugin_rspShifted[7 : 0] = execute_MEMORY_READ_DATA[31 : 24]; + end + default : begin + end + endcase + end + + assign _zz_83_ = (execute_DBusSimplePlugin_rspShifted[7] && (! execute_INSTRUCTION[14])); + always @ (*) begin + _zz_84_[31] = _zz_83_; + _zz_84_[30] = _zz_83_; + _zz_84_[29] = _zz_83_; + _zz_84_[28] = _zz_83_; + _zz_84_[27] = _zz_83_; + _zz_84_[26] = _zz_83_; + _zz_84_[25] = _zz_83_; + _zz_84_[24] = _zz_83_; + _zz_84_[23] = _zz_83_; + _zz_84_[22] = _zz_83_; + _zz_84_[21] = _zz_83_; + _zz_84_[20] = _zz_83_; + _zz_84_[19] = _zz_83_; + _zz_84_[18] = _zz_83_; + _zz_84_[17] = _zz_83_; + _zz_84_[16] = _zz_83_; + _zz_84_[15] = _zz_83_; + _zz_84_[14] = _zz_83_; + _zz_84_[13] = _zz_83_; + _zz_84_[12] = _zz_83_; + _zz_84_[11] = _zz_83_; + _zz_84_[10] = _zz_83_; + _zz_84_[9] = _zz_83_; + _zz_84_[8] = _zz_83_; + _zz_84_[7 : 0] = execute_DBusSimplePlugin_rspShifted[7 : 0]; + end + + assign _zz_85_ = (execute_DBusSimplePlugin_rspShifted[15] && (! execute_INSTRUCTION[14])); + always @ (*) begin + _zz_86_[31] = _zz_85_; + _zz_86_[30] = _zz_85_; + _zz_86_[29] = _zz_85_; + _zz_86_[28] = _zz_85_; + _zz_86_[27] = _zz_85_; + _zz_86_[26] = _zz_85_; + _zz_86_[25] = _zz_85_; + _zz_86_[24] = _zz_85_; + _zz_86_[23] = _zz_85_; + _zz_86_[22] = _zz_85_; + _zz_86_[21] = _zz_85_; + _zz_86_[20] = _zz_85_; + _zz_86_[19] = _zz_85_; + _zz_86_[18] = _zz_85_; + _zz_86_[17] = _zz_85_; + _zz_86_[16] = _zz_85_; + _zz_86_[15 : 0] = execute_DBusSimplePlugin_rspShifted[15 : 0]; + end + + always @ (*) begin + case(_zz_163_) + 2'b00 : begin + execute_DBusSimplePlugin_rspFormated = _zz_84_; + end + 2'b01 : begin + execute_DBusSimplePlugin_rspFormated = _zz_86_; + end + default : begin + execute_DBusSimplePlugin_rspFormated = execute_DBusSimplePlugin_rspShifted; + end + endcase + end + + assign _zz_88_ = ((decode_INSTRUCTION & (32'b00000000000000000000000000000100)) == (32'b00000000000000000000000000000100)); + assign _zz_89_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001001000)) == (32'b00000000000000000000000001001000)); + assign _zz_90_ = ((decode_INSTRUCTION & (32'b00000000000000000100000001010000)) == (32'b00000000000000000100000001010000)); + assign _zz_91_ = ((decode_INSTRUCTION & (32'b00000000000000000000000001010000)) == (32'b00000000000000000000000000010000)); + assign _zz_87_ = {(_zz_91_ != (1'b0)),{({_zz_206_,_zz_207_} != (2'b00)),{({_zz_208_,_zz_209_} != (6'b000000)),{(_zz_210_ != _zz_211_),{_zz_212_,{_zz_213_,_zz_214_}}}}}}; + assign _zz_58_ = ({((decode_INSTRUCTION & (32'b00000000000000000000000001011111)) == (32'b00000000000000000000000000010111)),{((decode_INSTRUCTION & (32'b00000000000000000000000001111111)) == (32'b00000000000000000000000001101111)),{((decode_INSTRUCTION & (32'b00000000000000000001000001101111)) == (32'b00000000000000000000000000000011)),{((decode_INSTRUCTION & _zz_321_) == (32'b00000000000000000001000001110011)),{(_zz_322_ == _zz_323_),{_zz_324_,{_zz_325_,_zz_326_}}}}}}} != (20'b00000000000000000000)); + assign _zz_57_ = _zz_169_[0]; + assign _zz_92_ = _zz_87_[4 : 3]; + assign _zz_56_ = _zz_92_; + assign _zz_93_ = _zz_87_[6 : 5]; + assign _zz_55_ = _zz_93_; + assign _zz_54_ = _zz_170_[0]; + assign _zz_94_ = _zz_87_[9 : 8]; + assign _zz_53_ = _zz_94_; + assign _zz_95_ = _zz_87_[11 : 10]; + assign _zz_52_ = _zz_95_; + assign _zz_96_ = _zz_87_[13 : 12]; + assign _zz_51_ = _zz_96_; + assign _zz_97_ = _zz_87_[17 : 16]; + assign _zz_50_ = _zz_97_; + assign _zz_49_ = _zz_171_[0]; + assign _zz_48_ = _zz_172_[0]; + assign _zz_47_ = _zz_173_[0]; + assign _zz_46_ = _zz_174_[0]; + assign _zz_98_ = _zz_87_[23 : 22]; + assign _zz_45_ = _zz_98_; + assign _zz_44_ = _zz_175_[0]; + assign _zz_43_ = _zz_176_[0]; + assign decodeExceptionPort_valid = ((decode_arbitration_isValid && decode_INSTRUCTION_READY) && (! decode_LEGAL_INSTRUCTION)); + assign decodeExceptionPort_payload_code = (4'b0010); + assign decodeExceptionPort_payload_badAddr = decode_INSTRUCTION; + assign execute_RegFilePlugin_regFileReadAddress1 = decode_INSTRUCTION[19 : 15]; + assign execute_RegFilePlugin_regFileReadAddress2 = decode_INSTRUCTION[24 : 20]; + assign _zz_99_ = (! execute_arbitration_isStuck); + assign execute_RegFilePlugin_rs1Data = _zz_148_; + assign execute_RegFilePlugin_rs2Data = _zz_149_; + assign _zz_42_ = execute_RegFilePlugin_rs1Data; + assign _zz_41_ = execute_RegFilePlugin_rs2Data; + assign execute_RegFilePlugin_regFileWrite_valid = (execute_REGFILE_WRITE_VALID && execute_arbitration_isFiring); + assign execute_RegFilePlugin_regFileWrite_payload_address = execute_INSTRUCTION[11 : 7]; + assign execute_RegFilePlugin_regFileWrite_payload_data = _zz_59_; + always @ (*) begin + case(execute_ALU_BITWISE_CTRL) + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : begin + execute_IntAluPlugin_bitwise = (execute_SRC1 & execute_SRC2); + end + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : begin + execute_IntAluPlugin_bitwise = (execute_SRC1 | execute_SRC2); + end + default : begin + execute_IntAluPlugin_bitwise = (execute_SRC1 ^ execute_SRC2); + end + endcase + end + + always @ (*) begin + case(execute_ALU_CTRL) + `AluCtrlEnum_defaultEncoding_BITWISE : begin + _zz_100_ = execute_IntAluPlugin_bitwise; + end + `AluCtrlEnum_defaultEncoding_SLT_SLTU : begin + _zz_100_ = {31'd0, _zz_177_}; + end + default : begin + _zz_100_ = execute_SRC_ADD_SUB; + end + endcase + end + + assign _zz_38_ = _zz_100_; + assign _zz_36_ = (decode_SRC_ADD_ZERO && (! decode_SRC_USE_SUB_LESS)); + always @ (*) begin + case(execute_SRC1_CTRL) + `Src1CtrlEnum_defaultEncoding_RS : begin + _zz_101_ = execute_RS1; + end + `Src1CtrlEnum_defaultEncoding_PC_INCREMENT : begin + _zz_101_ = {29'd0, _zz_178_}; + end + `Src1CtrlEnum_defaultEncoding_IMU : begin + _zz_101_ = {execute_INSTRUCTION[31 : 12],(12'b000000000000)}; + end + default : begin + _zz_101_ = {27'd0, _zz_179_}; + end + endcase + end + + assign _zz_35_ = _zz_101_; + assign _zz_102_ = _zz_180_[11]; + always @ (*) begin + _zz_103_[19] = _zz_102_; + _zz_103_[18] = _zz_102_; + _zz_103_[17] = _zz_102_; + _zz_103_[16] = _zz_102_; + _zz_103_[15] = _zz_102_; + _zz_103_[14] = _zz_102_; + _zz_103_[13] = _zz_102_; + _zz_103_[12] = _zz_102_; + _zz_103_[11] = _zz_102_; + _zz_103_[10] = _zz_102_; + _zz_103_[9] = _zz_102_; + _zz_103_[8] = _zz_102_; + _zz_103_[7] = _zz_102_; + _zz_103_[6] = _zz_102_; + _zz_103_[5] = _zz_102_; + _zz_103_[4] = _zz_102_; + _zz_103_[3] = _zz_102_; + _zz_103_[2] = _zz_102_; + _zz_103_[1] = _zz_102_; + _zz_103_[0] = _zz_102_; + end + + assign _zz_104_ = _zz_181_[11]; + always @ (*) begin + _zz_105_[19] = _zz_104_; + _zz_105_[18] = _zz_104_; + _zz_105_[17] = _zz_104_; + _zz_105_[16] = _zz_104_; + _zz_105_[15] = _zz_104_; + _zz_105_[14] = _zz_104_; + _zz_105_[13] = _zz_104_; + _zz_105_[12] = _zz_104_; + _zz_105_[11] = _zz_104_; + _zz_105_[10] = _zz_104_; + _zz_105_[9] = _zz_104_; + _zz_105_[8] = _zz_104_; + _zz_105_[7] = _zz_104_; + _zz_105_[6] = _zz_104_; + _zz_105_[5] = _zz_104_; + _zz_105_[4] = _zz_104_; + _zz_105_[3] = _zz_104_; + _zz_105_[2] = _zz_104_; + _zz_105_[1] = _zz_104_; + _zz_105_[0] = _zz_104_; + end + + always @ (*) begin + case(execute_SRC2_CTRL) + `Src2CtrlEnum_defaultEncoding_RS : begin + _zz_106_ = execute_RS2; + end + `Src2CtrlEnum_defaultEncoding_IMI : begin + _zz_106_ = {_zz_103_,execute_INSTRUCTION[31 : 20]}; + end + `Src2CtrlEnum_defaultEncoding_IMS : begin + _zz_106_ = {_zz_105_,{execute_INSTRUCTION[31 : 25],execute_INSTRUCTION[11 : 7]}}; + end + default : begin + _zz_106_ = execute_PC; + end + endcase + end + + assign _zz_33_ = _zz_106_; + always @ (*) begin + execute_SrcPlugin_addSub = _zz_182_; + if(execute_SRC2_FORCE_ZERO)begin + execute_SrcPlugin_addSub = execute_SRC1; + end + end + + assign execute_SrcPlugin_less = ((execute_SRC1[31] == execute_SRC2[31]) ? execute_SrcPlugin_addSub[31] : (execute_SRC_LESS_UNSIGNED ? execute_SRC2[31] : execute_SRC1[31])); + assign _zz_31_ = execute_SrcPlugin_addSub; + assign _zz_30_ = execute_SrcPlugin_addSub; + assign _zz_29_ = execute_SrcPlugin_less; + assign execute_LightShifterPlugin_isShift = (execute_SHIFT_CTRL != `ShiftCtrlEnum_defaultEncoding_DISABLE_1); + assign execute_LightShifterPlugin_amplitude = (execute_LightShifterPlugin_isActive ? execute_LightShifterPlugin_amplitudeReg : execute_SRC2[4 : 0]); + assign execute_LightShifterPlugin_shiftInput = (execute_LightShifterPlugin_isActive ? execute_LightShifterPlugin_shiftReg : execute_SRC1); + assign execute_LightShifterPlugin_done = (execute_LightShifterPlugin_amplitude[4 : 1] == (4'b0000)); + always @ (*) begin + case(execute_SHIFT_CTRL) + `ShiftCtrlEnum_defaultEncoding_SLL_1 : begin + _zz_107_ = (execute_LightShifterPlugin_shiftInput <<< 1); + end + default : begin + _zz_107_ = _zz_189_; + end + endcase + end + + assign execute_BranchPlugin_eq = (execute_SRC1 == execute_SRC2); + assign _zz_108_ = execute_INSTRUCTION[14 : 12]; + always @ (*) begin + if((_zz_108_ == (3'b000))) begin + _zz_109_ = execute_BranchPlugin_eq; + end else if((_zz_108_ == (3'b001))) begin + _zz_109_ = (! execute_BranchPlugin_eq); + end else if((((_zz_108_ & (3'b101)) == (3'b101)))) begin + _zz_109_ = (! execute_SRC_LESS); + end else begin + _zz_109_ = execute_SRC_LESS; + end + end + + always @ (*) begin + case(execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_INC : begin + _zz_110_ = 1'b0; + end + `BranchCtrlEnum_defaultEncoding_JAL : begin + _zz_110_ = 1'b1; + end + `BranchCtrlEnum_defaultEncoding_JALR : begin + _zz_110_ = 1'b1; + end + default : begin + _zz_110_ = _zz_109_; + end + endcase + end + + assign _zz_27_ = _zz_110_; + assign execute_BranchPlugin_branch_src1 = ((execute_BRANCH_CTRL == `BranchCtrlEnum_defaultEncoding_JALR) ? execute_RS1 : execute_PC); + assign _zz_111_ = _zz_191_[19]; + always @ (*) begin + _zz_112_[10] = _zz_111_; + _zz_112_[9] = _zz_111_; + _zz_112_[8] = _zz_111_; + _zz_112_[7] = _zz_111_; + _zz_112_[6] = _zz_111_; + _zz_112_[5] = _zz_111_; + _zz_112_[4] = _zz_111_; + _zz_112_[3] = _zz_111_; + _zz_112_[2] = _zz_111_; + _zz_112_[1] = _zz_111_; + _zz_112_[0] = _zz_111_; + end + + assign _zz_113_ = _zz_192_[11]; + always @ (*) begin + _zz_114_[19] = _zz_113_; + _zz_114_[18] = _zz_113_; + _zz_114_[17] = _zz_113_; + _zz_114_[16] = _zz_113_; + _zz_114_[15] = _zz_113_; + _zz_114_[14] = _zz_113_; + _zz_114_[13] = _zz_113_; + _zz_114_[12] = _zz_113_; + _zz_114_[11] = _zz_113_; + _zz_114_[10] = _zz_113_; + _zz_114_[9] = _zz_113_; + _zz_114_[8] = _zz_113_; + _zz_114_[7] = _zz_113_; + _zz_114_[6] = _zz_113_; + _zz_114_[5] = _zz_113_; + _zz_114_[4] = _zz_113_; + _zz_114_[3] = _zz_113_; + _zz_114_[2] = _zz_113_; + _zz_114_[1] = _zz_113_; + _zz_114_[0] = _zz_113_; + end + + assign _zz_115_ = _zz_193_[11]; + always @ (*) begin + _zz_116_[18] = _zz_115_; + _zz_116_[17] = _zz_115_; + _zz_116_[16] = _zz_115_; + _zz_116_[15] = _zz_115_; + _zz_116_[14] = _zz_115_; + _zz_116_[13] = _zz_115_; + _zz_116_[12] = _zz_115_; + _zz_116_[11] = _zz_115_; + _zz_116_[10] = _zz_115_; + _zz_116_[9] = _zz_115_; + _zz_116_[8] = _zz_115_; + _zz_116_[7] = _zz_115_; + _zz_116_[6] = _zz_115_; + _zz_116_[5] = _zz_115_; + _zz_116_[4] = _zz_115_; + _zz_116_[3] = _zz_115_; + _zz_116_[2] = _zz_115_; + _zz_116_[1] = _zz_115_; + _zz_116_[0] = _zz_115_; + end + + always @ (*) begin + case(execute_BRANCH_CTRL) + `BranchCtrlEnum_defaultEncoding_JAL : begin + _zz_117_ = {{_zz_112_,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[19 : 12]},execute_INSTRUCTION[20]},execute_INSTRUCTION[30 : 21]}},1'b0}; + end + `BranchCtrlEnum_defaultEncoding_JALR : begin + _zz_117_ = {_zz_114_,execute_INSTRUCTION[31 : 20]}; + end + default : begin + _zz_117_ = {{_zz_116_,{{{execute_INSTRUCTION[31],execute_INSTRUCTION[7]},execute_INSTRUCTION[30 : 25]},execute_INSTRUCTION[11 : 8]}},1'b0}; + end + endcase + end + + assign execute_BranchPlugin_branch_src2 = _zz_117_; + assign execute_BranchPlugin_branchAdder = (execute_BranchPlugin_branch_src1 + execute_BranchPlugin_branch_src2); + assign _zz_25_ = {execute_BranchPlugin_branchAdder[31 : 1],(1'b0)}; + assign BranchPlugin_jumpInterface_valid = ((execute_arbitration_isValid && (! execute_arbitration_isStuckByOthers)) && execute_BRANCH_DO); + assign BranchPlugin_jumpInterface_payload = execute_BRANCH_CALC; + always @ (*) begin + BranchPlugin_branchExceptionPort_valid = ((execute_arbitration_isValid && execute_BRANCH_DO) && BranchPlugin_jumpInterface_payload[1]); + if(1'b0)begin + BranchPlugin_branchExceptionPort_valid = 1'b0; + end + end + + assign BranchPlugin_branchExceptionPort_payload_code = (4'b0000); + assign BranchPlugin_branchExceptionPort_payload_badAddr = BranchPlugin_jumpInterface_payload; + always @ (*) begin + CsrPlugin_privilege = (2'b11); + if(CsrPlugin_forceMachineWire)begin + CsrPlugin_privilege = (2'b11); + end + end + + assign CsrPlugin_misa_base = (2'b01); + assign CsrPlugin_misa_extensions = (26'b00000000000000000000000000); + assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped = (2'b11); + assign CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege = ((CsrPlugin_privilege < CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped) ? CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilegeUncapped : CsrPlugin_privilege); + assign _zz_118_ = {decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid}; + assign _zz_119_ = _zz_194_[0]; + assign _zz_120_ = {CsrPlugin_selfException_valid,{BranchPlugin_branchExceptionPort_valid,DBusSimplePlugin_memoryExceptionPort_valid}}; + assign _zz_121_ = (_zz_120_ & (~ _zz_196_)); + assign _zz_122_ = _zz_121_[1]; + assign _zz_123_ = _zz_121_[2]; + assign _zz_124_ = {_zz_123_,_zz_122_}; + always @ (*) begin + CsrPlugin_exceptionPortCtrl_exceptionValids_decode = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; + if(_zz_155_)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b1; + end + if(decode_arbitration_isFlushed)begin + CsrPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b0; + end + end + + assign CsrPlugin_exceptionPendings_0 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; + assign CsrPlugin_exceptionPendings_1 = CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; + always @ (*) begin + CsrPlugin_interrupt = 1'b0; + CsrPlugin_interruptCode = (4'bxxxx); + CsrPlugin_interruptTargetPrivilege = (2'bxx); + if((CsrPlugin_mstatus_MIE || (CsrPlugin_privilege < (2'b11))))begin + if((((CsrPlugin_mip_MTIP && CsrPlugin_mie_MTIE) && 1'b1) && (! 1'b0)))begin + CsrPlugin_interrupt = 1'b1; + CsrPlugin_interruptCode = (4'b0111); + CsrPlugin_interruptTargetPrivilege = (2'b11); + end + if((((CsrPlugin_mip_MSIP && CsrPlugin_mie_MSIE) && 1'b1) && (! 1'b0)))begin + CsrPlugin_interrupt = 1'b1; + CsrPlugin_interruptCode = (4'b0011); + CsrPlugin_interruptTargetPrivilege = (2'b11); + end + if((((CsrPlugin_mip_MEIP && CsrPlugin_mie_MEIE) && 1'b1) && (! 1'b0)))begin + CsrPlugin_interrupt = 1'b1; + CsrPlugin_interruptCode = (4'b1011); + CsrPlugin_interruptTargetPrivilege = (2'b11); + end + end + if((! CsrPlugin_allowInterrupts))begin + CsrPlugin_interrupt = 1'b0; + end + end + + assign CsrPlugin_exception = (CsrPlugin_exceptionPortCtrl_exceptionValids_execute && CsrPlugin_allowException); + assign CsrPlugin_lastStageWasWfi = 1'b0; + always @ (*) begin + CsrPlugin_pipelineLiberator_done = ((! (execute_arbitration_isValid != (1'b0))) && IBusCachedPlugin_pcValids_1); + if((CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute != (1'b0)))begin + CsrPlugin_pipelineLiberator_done = 1'b0; + end + if(CsrPlugin_hadException)begin + CsrPlugin_pipelineLiberator_done = 1'b0; + end + end + + assign CsrPlugin_interruptJump = (CsrPlugin_interrupt && CsrPlugin_pipelineLiberator_done); + always @ (*) begin + CsrPlugin_targetPrivilege = CsrPlugin_interruptTargetPrivilege; + if(CsrPlugin_hadException)begin + CsrPlugin_targetPrivilege = CsrPlugin_exceptionPortCtrl_exceptionTargetPrivilege; + end + end + + always @ (*) begin + CsrPlugin_trapCause = CsrPlugin_interruptCode; + if(CsrPlugin_hadException)begin + CsrPlugin_trapCause = CsrPlugin_exceptionPortCtrl_exceptionContext_code; + end + end + + always @ (*) begin + CsrPlugin_xtvec_mode = (2'bxx); + CsrPlugin_xtvec_base = (30'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx); + case(CsrPlugin_targetPrivilege) + 2'b11 : begin + CsrPlugin_xtvec_mode = CsrPlugin_mtvec_mode; + CsrPlugin_xtvec_base = CsrPlugin_mtvec_base; + end + default : begin + end + endcase + end + + assign contextSwitching = CsrPlugin_jumpInterface_valid; + assign _zz_23_ = (! (((decode_INSTRUCTION[14 : 13] == (2'b01)) && (decode_INSTRUCTION[19 : 15] == (5'b00000))) || ((decode_INSTRUCTION[14 : 13] == (2'b11)) && (decode_INSTRUCTION[19 : 15] == (5'b00000))))); + assign _zz_22_ = (decode_INSTRUCTION[13 : 7] != (7'b0100000)); + assign execute_CsrPlugin_inWfi = 1'b0; + assign execute_CsrPlugin_blockedBySideEffects = 1'b0; + always @ (*) begin + execute_CsrPlugin_illegalAccess = 1'b1; + execute_CsrPlugin_readData = (32'b00000000000000000000000000000000); + case(execute_CsrPlugin_csrAddress) + 12'b101111000000 : begin + execute_CsrPlugin_illegalAccess = 1'b0; + execute_CsrPlugin_readData[31 : 0] = _zz_125_; + end + 12'b001100000000 : begin + execute_CsrPlugin_illegalAccess = 1'b0; + execute_CsrPlugin_readData[12 : 11] = CsrPlugin_mstatus_MPP; + execute_CsrPlugin_readData[7 : 7] = CsrPlugin_mstatus_MPIE; + execute_CsrPlugin_readData[3 : 3] = CsrPlugin_mstatus_MIE; + end + 12'b001101000001 : begin + execute_CsrPlugin_illegalAccess = 1'b0; + execute_CsrPlugin_readData[31 : 0] = CsrPlugin_mepc; + end + 12'b001100000101 : begin + if(execute_CSR_WRITE_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + 12'b001101000100 : begin + execute_CsrPlugin_illegalAccess = 1'b0; + execute_CsrPlugin_readData[11 : 11] = CsrPlugin_mip_MEIP; + execute_CsrPlugin_readData[7 : 7] = CsrPlugin_mip_MTIP; + execute_CsrPlugin_readData[3 : 3] = CsrPlugin_mip_MSIP; + end + 12'b001101000011 : begin + if(execute_CSR_READ_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + execute_CsrPlugin_readData[31 : 0] = CsrPlugin_mtval; + end + 12'b111111000000 : begin + if(execute_CSR_READ_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + execute_CsrPlugin_readData[31 : 0] = _zz_126_; + end + 12'b001101000000 : begin + execute_CsrPlugin_illegalAccess = 1'b0; + execute_CsrPlugin_readData[31 : 0] = CsrPlugin_mscratch; + end + 12'b001100000100 : begin + execute_CsrPlugin_illegalAccess = 1'b0; + execute_CsrPlugin_readData[11 : 11] = CsrPlugin_mie_MEIE; + execute_CsrPlugin_readData[7 : 7] = CsrPlugin_mie_MTIE; + execute_CsrPlugin_readData[3 : 3] = CsrPlugin_mie_MSIE; + end + 12'b001101000010 : begin + if(execute_CSR_READ_OPCODE)begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + execute_CsrPlugin_readData[31 : 31] = CsrPlugin_mcause_interrupt; + execute_CsrPlugin_readData[3 : 0] = CsrPlugin_mcause_exceptionCode; + end + default : begin + end + endcase + if((CsrPlugin_privilege < execute_CsrPlugin_csrAddress[9 : 8]))begin + execute_CsrPlugin_illegalAccess = 1'b1; + end + if(((! execute_arbitration_isValid) || (! execute_IS_CSR)))begin + execute_CsrPlugin_illegalAccess = 1'b0; + end + end + + always @ (*) begin + execute_CsrPlugin_illegalInstruction = 1'b0; + if((execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_XRET)))begin + if((CsrPlugin_privilege < execute_INSTRUCTION[29 : 28]))begin + execute_CsrPlugin_illegalInstruction = 1'b1; + end + end + end + + always @ (*) begin + CsrPlugin_selfException_valid = 1'b0; + CsrPlugin_selfException_payload_code = (4'bxxxx); + if((execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_ECALL)))begin + CsrPlugin_selfException_valid = 1'b1; + case(CsrPlugin_privilege) + 2'b00 : begin + CsrPlugin_selfException_payload_code = (4'b1000); + end + default : begin + CsrPlugin_selfException_payload_code = (4'b1011); + end + endcase + end + if((execute_arbitration_isValid && (execute_ENV_CTRL == `EnvCtrlEnum_defaultEncoding_EBREAK)))begin + CsrPlugin_selfException_valid = 1'b1; + CsrPlugin_selfException_payload_code = (4'b0011); + end + end + + assign CsrPlugin_selfException_payload_badAddr = execute_INSTRUCTION; + assign execute_CsrPlugin_writeInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_WRITE_OPCODE); + assign execute_CsrPlugin_readInstruction = ((execute_arbitration_isValid && execute_IS_CSR) && execute_CSR_READ_OPCODE); + assign execute_CsrPlugin_writeEnable = ((execute_CsrPlugin_writeInstruction && (! execute_CsrPlugin_blockedBySideEffects)) && (! execute_arbitration_isStuckByOthers)); + assign execute_CsrPlugin_readEnable = ((execute_CsrPlugin_readInstruction && (! execute_CsrPlugin_blockedBySideEffects)) && (! execute_arbitration_isStuckByOthers)); + assign execute_CsrPlugin_readToWriteData = execute_CsrPlugin_readData; + always @ (*) begin + case(_zz_164_) + 1'b0 : begin + execute_CsrPlugin_writeData = execute_SRC1; + end + default : begin + execute_CsrPlugin_writeData = (execute_INSTRUCTION[12] ? (execute_CsrPlugin_readToWriteData & (~ execute_SRC1)) : (execute_CsrPlugin_readToWriteData | execute_SRC1)); + end + endcase + end + + assign execute_CsrPlugin_csrAddress = execute_INSTRUCTION[31 : 20]; + assign _zz_126_ = (_zz_125_ & externalInterruptArray_regNext); + assign externalInterrupt = (_zz_126_ != (32'b00000000000000000000000000000000)); + assign _zz_21_ = decode_ALU_BITWISE_CTRL; + assign _zz_19_ = _zz_45_; + assign _zz_39_ = decode_to_execute_ALU_BITWISE_CTRL; + assign _zz_18_ = decode_SHIFT_CTRL; + assign _zz_16_ = _zz_56_; + assign _zz_28_ = decode_to_execute_SHIFT_CTRL; + assign _zz_15_ = decode_BRANCH_CTRL; + assign _zz_13_ = _zz_51_; + assign _zz_26_ = decode_to_execute_BRANCH_CTRL; + assign _zz_12_ = decode_ALU_CTRL; + assign _zz_10_ = _zz_53_; + assign _zz_37_ = decode_to_execute_ALU_CTRL; + assign _zz_9_ = decode_SRC1_CTRL; + assign _zz_7_ = _zz_50_; + assign _zz_34_ = decode_to_execute_SRC1_CTRL; + assign _zz_6_ = decode_SRC2_CTRL; + assign _zz_4_ = _zz_55_; + assign _zz_32_ = decode_to_execute_SRC2_CTRL; + assign _zz_3_ = decode_ENV_CTRL; + assign _zz_1_ = _zz_52_; + assign _zz_24_ = decode_to_execute_ENV_CTRL; + assign decode_arbitration_isFlushed = ({execute_arbitration_flushAll,decode_arbitration_flushAll} != (2'b00)); + assign execute_arbitration_isFlushed = (execute_arbitration_flushAll != (1'b0)); + assign decode_arbitration_isStuckByOthers = (decode_arbitration_haltByOther || (1'b0 || execute_arbitration_isStuck)); + assign decode_arbitration_isStuck = (decode_arbitration_haltItself || decode_arbitration_isStuckByOthers); + assign decode_arbitration_isMoving = ((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)); + assign decode_arbitration_isFiring = ((decode_arbitration_isValid && (! decode_arbitration_isStuck)) && (! decode_arbitration_removeIt)); + assign execute_arbitration_isStuckByOthers = (execute_arbitration_haltByOther || 1'b0); + assign execute_arbitration_isStuck = (execute_arbitration_haltItself || execute_arbitration_isStuckByOthers); + assign execute_arbitration_isMoving = ((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)); + assign execute_arbitration_isFiring = ((execute_arbitration_isValid && (! execute_arbitration_isStuck)) && (! execute_arbitration_removeIt)); + assign iBusWishbone_ADR = {_zz_203_,_zz_127_}; + assign iBusWishbone_CTI = ((_zz_127_ == (3'b111)) ? (3'b111) : (3'b010)); + assign iBusWishbone_BTE = (2'b00); + assign iBusWishbone_SEL = (4'b1111); + assign iBusWishbone_WE = 1'b0; + assign iBusWishbone_DAT_MOSI = (32'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx); + always @ (*) begin + iBusWishbone_CYC = 1'b0; + iBusWishbone_STB = 1'b0; + if(_zz_161_)begin + iBusWishbone_CYC = 1'b1; + iBusWishbone_STB = 1'b1; + end + end + + assign iBus_cmd_ready = (iBus_cmd_valid && iBusWishbone_ACK); + assign iBus_rsp_valid = _zz_128_; + assign iBus_rsp_payload_data = iBusWishbone_DAT_MISO_regNext; + assign iBus_rsp_payload_error = 1'b0; + assign dBus_cmd_halfPipe_valid = dBus_cmd_halfPipe_regs_valid; + assign dBus_cmd_halfPipe_payload_wr = dBus_cmd_halfPipe_regs_payload_wr; + assign dBus_cmd_halfPipe_payload_address = dBus_cmd_halfPipe_regs_payload_address; + assign dBus_cmd_halfPipe_payload_data = dBus_cmd_halfPipe_regs_payload_data; + assign dBus_cmd_halfPipe_payload_size = dBus_cmd_halfPipe_regs_payload_size; + assign dBus_cmd_ready = dBus_cmd_halfPipe_regs_ready; + assign dBusWishbone_ADR = (dBus_cmd_halfPipe_payload_address >>> 2); + assign dBusWishbone_CTI = (3'b000); + assign dBusWishbone_BTE = (2'b00); + always @ (*) begin + case(dBus_cmd_halfPipe_payload_size) + 2'b00 : begin + _zz_129_ = (4'b0001); + end + 2'b01 : begin + _zz_129_ = (4'b0011); + end + default : begin + _zz_129_ = (4'b1111); + end + endcase + end + + always @ (*) begin + dBusWishbone_SEL = _zz_204_[3:0]; + if((! dBus_cmd_halfPipe_payload_wr))begin + dBusWishbone_SEL = (4'b1111); + end + end + + assign dBusWishbone_WE = dBus_cmd_halfPipe_payload_wr; + assign dBusWishbone_DAT_MOSI = dBus_cmd_halfPipe_payload_data; + assign dBus_cmd_halfPipe_ready = (dBus_cmd_halfPipe_valid && dBusWishbone_ACK); + assign dBusWishbone_CYC = dBus_cmd_halfPipe_valid; + assign dBusWishbone_STB = dBus_cmd_halfPipe_valid; + assign dBus_rsp_ready = ((dBus_cmd_halfPipe_valid && (! dBusWishbone_WE)) && dBusWishbone_ACK); + assign dBus_rsp_data = dBusWishbone_DAT_MISO; + assign dBus_rsp_error = 1'b0; + always @ (posedge clk) begin + if(reset) begin + IBusCachedPlugin_fetchPc_pcReg <= externalResetVector; + IBusCachedPlugin_fetchPc_inc <= 1'b0; + _zz_75_ <= 1'b0; + _zz_80_ <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; + IBusCachedPlugin_injector_decodeRemoved <= 1'b0; + execute_DBusSimplePlugin_cmdSent <= 1'b0; + execute_LightShifterPlugin_isActive <= 1'b0; + CsrPlugin_mstatus_MIE <= 1'b0; + CsrPlugin_mstatus_MPIE <= 1'b0; + CsrPlugin_mstatus_MPP <= (2'b11); + CsrPlugin_mie_MEIE <= 1'b0; + CsrPlugin_mie_MTIE <= 1'b0; + CsrPlugin_mie_MSIE <= 1'b0; + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0; + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= 1'b0; + CsrPlugin_hadException <= 1'b0; + _zz_125_ <= (32'b00000000000000000000000000000000); + execute_arbitration_isValid <= 1'b0; + _zz_127_ <= (3'b000); + _zz_128_ <= 1'b0; + dBus_cmd_halfPipe_regs_valid <= 1'b0; + dBus_cmd_halfPipe_regs_ready <= 1'b1; + end else begin + if(IBusCachedPlugin_fetchPc_propagatePc)begin + IBusCachedPlugin_fetchPc_inc <= 1'b0; + end + if(IBusCachedPlugin_jump_pcLoad_valid)begin + IBusCachedPlugin_fetchPc_inc <= 1'b0; + end + if(_zz_160_)begin + IBusCachedPlugin_fetchPc_inc <= 1'b1; + end + if(IBusCachedPlugin_fetchPc_samplePcNext)begin + IBusCachedPlugin_fetchPc_pcReg <= IBusCachedPlugin_fetchPc_pc; + end + _zz_75_ <= 1'b1; + if((IBusCachedPlugin_jump_pcLoad_valid || IBusCachedPlugin_fetcherflushIt))begin + _zz_80_ <= 1'b0; + end + if(_zz_78_)begin + _zz_80_ <= IBusCachedPlugin_iBusRsp_stages_0_output_valid; + end + if((IBusCachedPlugin_jump_pcLoad_valid || IBusCachedPlugin_fetcherflushIt))begin + IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0; + end + if((! (! IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready)))begin + IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b1; + end + if((IBusCachedPlugin_jump_pcLoad_valid || IBusCachedPlugin_fetcherflushIt))begin + IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; + end + if((! execute_arbitration_isStuck))begin + IBusCachedPlugin_injector_nextPcCalc_valids_1 <= IBusCachedPlugin_injector_nextPcCalc_valids_0; + end + if((IBusCachedPlugin_jump_pcLoad_valid || IBusCachedPlugin_fetcherflushIt))begin + IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; + end + if(decode_arbitration_removeIt)begin + IBusCachedPlugin_injector_decodeRemoved <= 1'b1; + end + if((IBusCachedPlugin_jump_pcLoad_valid || IBusCachedPlugin_fetcherflushIt))begin + IBusCachedPlugin_injector_decodeRemoved <= 1'b0; + end + if((dBus_cmd_valid && dBus_cmd_ready))begin + execute_DBusSimplePlugin_cmdSent <= 1'b1; + end + if((! execute_arbitration_isStuck))begin + execute_DBusSimplePlugin_cmdSent <= 1'b0; + end + if(_zz_153_)begin + if(_zz_154_)begin + execute_LightShifterPlugin_isActive <= 1'b1; + if(execute_LightShifterPlugin_done)begin + execute_LightShifterPlugin_isActive <= 1'b0; + end + end + end + if(execute_arbitration_removeIt)begin + execute_LightShifterPlugin_isActive <= 1'b0; + end + if((! decode_arbitration_isStuck))begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0; + end else begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= CsrPlugin_exceptionPortCtrl_exceptionValids_decode; + end + if((! execute_arbitration_isStuck))begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= (CsrPlugin_exceptionPortCtrl_exceptionValids_decode && (! decode_arbitration_isStuck)); + end else begin + CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= 1'b0; + end + CsrPlugin_hadException <= CsrPlugin_exception; + if(_zz_157_)begin + case(CsrPlugin_targetPrivilege) + 2'b11 : begin + CsrPlugin_mstatus_MIE <= 1'b0; + CsrPlugin_mstatus_MPIE <= CsrPlugin_mstatus_MIE; + CsrPlugin_mstatus_MPP <= CsrPlugin_privilege; + end + default : begin + end + endcase + end + if(_zz_158_)begin + case(_zz_159_) + 2'b11 : begin + CsrPlugin_mstatus_MPP <= (2'b00); + CsrPlugin_mstatus_MIE <= CsrPlugin_mstatus_MPIE; + CsrPlugin_mstatus_MPIE <= 1'b1; + end + default : begin + end + endcase + end + if(((! execute_arbitration_isStuck) || execute_arbitration_removeIt))begin + execute_arbitration_isValid <= 1'b0; + end + if(((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)))begin + execute_arbitration_isValid <= decode_arbitration_isValid; + end + case(execute_CsrPlugin_csrAddress) + 12'b101111000000 : begin + if(execute_CsrPlugin_writeEnable)begin + _zz_125_ <= execute_CsrPlugin_writeData[31 : 0]; + end + end + 12'b001100000000 : begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mstatus_MPP <= execute_CsrPlugin_writeData[12 : 11]; + CsrPlugin_mstatus_MPIE <= _zz_197_[0]; + CsrPlugin_mstatus_MIE <= _zz_198_[0]; + end + end + 12'b001101000001 : begin + end + 12'b001100000101 : begin + end + 12'b001101000100 : begin + end + 12'b001101000011 : begin + end + 12'b111111000000 : begin + end + 12'b001101000000 : begin + end + 12'b001100000100 : begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mie_MEIE <= _zz_200_[0]; + CsrPlugin_mie_MTIE <= _zz_201_[0]; + CsrPlugin_mie_MSIE <= _zz_202_[0]; + end + end + 12'b001101000010 : begin + end + default : begin + end + endcase + if(_zz_161_)begin + if(iBusWishbone_ACK)begin + _zz_127_ <= (_zz_127_ + (3'b001)); + end + end + _zz_128_ <= (iBusWishbone_CYC && iBusWishbone_ACK); + if(_zz_162_)begin + dBus_cmd_halfPipe_regs_valid <= dBus_cmd_valid; + dBus_cmd_halfPipe_regs_ready <= (! dBus_cmd_valid); + end else begin + dBus_cmd_halfPipe_regs_valid <= (! dBus_cmd_halfPipe_ready); + dBus_cmd_halfPipe_regs_ready <= dBus_cmd_halfPipe_ready; + end + end + end + + always @ (posedge clk) begin + if(IBusCachedPlugin_iBusRsp_cacheRspArbitration_input_ready)begin + IBusCachedPlugin_s1_tightlyCoupledHit <= IBusCachedPlugin_s0_tightlyCoupledHit; + end + if((! execute_arbitration_isStuckByOthers))begin + execute_LightShifterPlugin_shiftReg <= _zz_59_; + end + if(_zz_153_)begin + if(_zz_154_)begin + execute_LightShifterPlugin_amplitudeReg <= (execute_LightShifterPlugin_amplitude - (5'b00001)); + end + end + CsrPlugin_mip_MEIP <= externalInterrupt; + CsrPlugin_mip_MTIP <= timerInterrupt; + CsrPlugin_mip_MSIP <= softwareInterrupt; + CsrPlugin_mcycle <= (CsrPlugin_mcycle + (64'b0000000000000000000000000000000000000000000000000000000000000001)); + if(execute_arbitration_isFiring)begin + CsrPlugin_minstret <= (CsrPlugin_minstret + (64'b0000000000000000000000000000000000000000000000000000000000000001)); + end + if(_zz_155_)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_119_ ? IBusCachedPlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_119_ ? IBusCachedPlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); + end + if(_zz_156_)begin + CsrPlugin_exceptionPortCtrl_exceptionContext_code <= _zz_151_; + CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr <= _zz_152_; + end + if(_zz_157_)begin + case(CsrPlugin_targetPrivilege) + 2'b11 : begin + CsrPlugin_mcause_interrupt <= (! CsrPlugin_hadException); + CsrPlugin_mcause_exceptionCode <= CsrPlugin_trapCause; + CsrPlugin_mepc <= execute_PC; + if(CsrPlugin_hadException)begin + CsrPlugin_mtval <= CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr; + end + end + default : begin + end + endcase + end + externalInterruptArray_regNext <= externalInterruptArray; + if((! execute_arbitration_isStuck))begin + decode_to_execute_ALU_BITWISE_CTRL <= _zz_20_; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SHIFT_CTRL <= _zz_17_; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_BRANCH_CTRL <= _zz_14_; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_MEMORY_STORE <= decode_MEMORY_STORE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC2_FORCE_ZERO <= decode_SRC2_FORCE_ZERO; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_ALU_CTRL <= _zz_11_; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC_USE_SUB_LESS <= decode_SRC_USE_SUB_LESS; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_REGFILE_WRITE_VALID <= decode_REGFILE_WRITE_VALID; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_CSR_READ_OPCODE <= decode_CSR_READ_OPCODE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC1_CTRL <= _zz_8_; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_MEMORY_ENABLE <= decode_MEMORY_ENABLE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_IS_CSR <= decode_IS_CSR; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC2_CTRL <= _zz_5_; + end + if(((! execute_arbitration_isStuck) && (! CsrPlugin_exceptionPortCtrl_exceptionValids_execute)))begin + decode_to_execute_PC <= decode_PC; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_INSTRUCTION <= decode_INSTRUCTION; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_FORMAL_PC_NEXT <= _zz_66_; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_ENV_CTRL <= _zz_2_; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_SRC_LESS_UNSIGNED <= decode_SRC_LESS_UNSIGNED; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_CSR_WRITE_OPCODE <= decode_CSR_WRITE_OPCODE; + end + case(execute_CsrPlugin_csrAddress) + 12'b101111000000 : begin + end + 12'b001100000000 : begin + end + 12'b001101000001 : begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mepc <= execute_CsrPlugin_writeData[31 : 0]; + end + end + 12'b001100000101 : begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mtvec_base <= execute_CsrPlugin_writeData[31 : 2]; + CsrPlugin_mtvec_mode <= execute_CsrPlugin_writeData[1 : 0]; + end + end + 12'b001101000100 : begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mip_MSIP <= _zz_199_[0]; + end + end + 12'b001101000011 : begin + end + 12'b111111000000 : begin + end + 12'b001101000000 : begin + if(execute_CsrPlugin_writeEnable)begin + CsrPlugin_mscratch <= execute_CsrPlugin_writeData[31 : 0]; + end + end + 12'b001100000100 : begin + end + 12'b001101000010 : begin + end + default : begin + end + endcase + iBusWishbone_DAT_MISO_regNext <= iBusWishbone_DAT_MISO; + if(_zz_162_)begin + dBus_cmd_halfPipe_regs_payload_wr <= dBus_cmd_payload_wr; + dBus_cmd_halfPipe_regs_payload_address <= dBus_cmd_payload_address; + dBus_cmd_halfPipe_regs_payload_data <= dBus_cmd_payload_data; + dBus_cmd_halfPipe_regs_payload_size <= dBus_cmd_payload_size; + end + end + +endmodule + diff --git a/rtl/spimemio.v b/rtl/spimemio.v new file mode 100644 index 0000000..0bbf532 --- /dev/null +++ b/rtl/spimemio.v @@ -0,0 +1,579 @@ +/* + * PicoSoC - A simple example SoC using PicoRV32 + * + * Copyright (C) 2017 Clifford Wolf + * + * Permission to use, copy, modify, and/or distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + * + */ + +module spimemio ( + input clk, resetn, + + input valid, + output ready, + input [23:0] addr, + output reg [31:0] rdata, + + output flash_csb, + output flash_clk, + + output flash_io0_oe, + output flash_io1_oe, + output flash_io2_oe, + output flash_io3_oe, + + output flash_io0_do, + output flash_io1_do, + output flash_io2_do, + output flash_io3_do, + + input flash_io0_di, + input flash_io1_di, + input flash_io2_di, + input flash_io3_di, + + input [3:0] cfgreg_we, + input [31:0] cfgreg_di, + output [31:0] cfgreg_do +); + reg xfer_resetn; + reg din_valid; + wire din_ready; + reg [7:0] din_data; + reg [3:0] din_tag; + reg din_cont; + reg din_qspi; + reg din_ddr; + reg din_rd; + + wire dout_valid; + wire [7:0] dout_data; + wire [3:0] dout_tag; + + reg [23:0] buffer; + + reg [23:0] rd_addr; + reg rd_valid; + reg rd_wait; + reg rd_inc; + + assign ready = valid && (addr == rd_addr) && rd_valid; + wire jump = valid && !ready && (addr != rd_addr+4) && rd_valid; + + reg softreset; + + reg config_en; // cfgreg[31] + reg config_ddr; // cfgreg[22] + reg config_qspi; // cfgreg[21] + reg config_cont; // cfgreg[20] + reg [3:0] config_dummy; // cfgreg[19:16] + reg [3:0] config_oe; // cfgreg[11:8] + reg config_csb; // cfgreg[5] + reg config_clk; // cfgref[4] + reg [3:0] config_do; // cfgreg[3:0] + + assign cfgreg_do[31] = config_en; + assign cfgreg_do[30:23] = 0; + assign cfgreg_do[22] = config_ddr; + assign cfgreg_do[21] = config_qspi; + assign cfgreg_do[20] = config_cont; + assign cfgreg_do[19:16] = config_dummy; + assign cfgreg_do[15:12] = 0; + assign cfgreg_do[11:8] = {flash_io3_oe, flash_io2_oe, flash_io1_oe, flash_io0_oe}; + assign cfgreg_do[7:6] = 0; + assign cfgreg_do[5] = flash_csb; + assign cfgreg_do[4] = flash_clk; + assign cfgreg_do[3:0] = {flash_io3_di, flash_io2_di, flash_io1_di, flash_io0_di}; + + always @(posedge clk) begin + softreset <= !config_en || cfgreg_we; + if (!resetn) begin + softreset <= 1; + config_en <= 1; + config_csb <= 0; + config_clk <= 0; + config_oe <= 0; + config_do <= 0; + config_ddr <= 0; + config_qspi <= 0; + config_cont <= 0; + config_dummy <= 8; + end else begin + if (cfgreg_we[0]) begin + config_csb <= cfgreg_di[5]; + config_clk <= cfgreg_di[4]; + config_do <= cfgreg_di[3:0]; + end + if (cfgreg_we[1]) begin + config_oe <= cfgreg_di[11:8]; + end + if (cfgreg_we[2]) begin + config_ddr <= cfgreg_di[22]; + config_qspi <= cfgreg_di[21]; + config_cont <= cfgreg_di[20]; + config_dummy <= cfgreg_di[19:16]; + end + if (cfgreg_we[3]) begin + config_en <= cfgreg_di[31]; + end + end + end + + wire xfer_csb; + wire xfer_clk; + + wire xfer_io0_oe; + wire xfer_io1_oe; + wire xfer_io2_oe; + wire xfer_io3_oe; + + wire xfer_io0_do; + wire xfer_io1_do; + wire xfer_io2_do; + wire xfer_io3_do; + + reg xfer_io0_90; + reg xfer_io1_90; + reg xfer_io2_90; + reg xfer_io3_90; + + always @(negedge clk) begin + xfer_io0_90 <= xfer_io0_do; + xfer_io1_90 <= xfer_io1_do; + xfer_io2_90 <= xfer_io2_do; + xfer_io3_90 <= xfer_io3_do; + end + + assign flash_csb = config_en ? xfer_csb : config_csb; + assign flash_clk = config_en ? xfer_clk : config_clk; + + assign flash_io0_oe = config_en ? xfer_io0_oe : config_oe[0]; + assign flash_io1_oe = config_en ? xfer_io1_oe : config_oe[1]; + assign flash_io2_oe = config_en ? xfer_io2_oe : config_oe[2]; + assign flash_io3_oe = config_en ? xfer_io3_oe : config_oe[3]; + + assign flash_io0_do = config_en ? (config_ddr ? xfer_io0_90 : xfer_io0_do) : config_do[0]; + assign flash_io1_do = config_en ? (config_ddr ? xfer_io1_90 : xfer_io1_do) : config_do[1]; + assign flash_io2_do = config_en ? (config_ddr ? xfer_io2_90 : xfer_io2_do) : config_do[2]; + assign flash_io3_do = config_en ? (config_ddr ? xfer_io3_90 : xfer_io3_do) : config_do[3]; + + wire xfer_dspi = din_ddr && !din_qspi; + wire xfer_ddr = din_ddr && din_qspi; + + spimemio_xfer xfer ( + .clk (clk ), + .resetn (xfer_resetn ), + .din_valid (din_valid ), + .din_ready (din_ready ), + .din_data (din_data ), + .din_tag (din_tag ), + .din_cont (din_cont ), + .din_dspi (xfer_dspi ), + .din_qspi (din_qspi ), + .din_ddr (xfer_ddr ), + .din_rd (din_rd ), + .dout_valid (dout_valid ), + .dout_data (dout_data ), + .dout_tag (dout_tag ), + .flash_csb (xfer_csb ), + .flash_clk (xfer_clk ), + .flash_io0_oe (xfer_io0_oe ), + .flash_io1_oe (xfer_io1_oe ), + .flash_io2_oe (xfer_io2_oe ), + .flash_io3_oe (xfer_io3_oe ), + .flash_io0_do (xfer_io0_do ), + .flash_io1_do (xfer_io1_do ), + .flash_io2_do (xfer_io2_do ), + .flash_io3_do (xfer_io3_do ), + .flash_io0_di (flash_io0_di), + .flash_io1_di (flash_io1_di), + .flash_io2_di (flash_io2_di), + .flash_io3_di (flash_io3_di) + ); + + reg [3:0] state; + + always @(posedge clk) begin + xfer_resetn <= 1; + din_valid <= 0; + + if (!resetn || softreset) begin + state <= 0; + xfer_resetn <= 0; + rd_valid <= 0; + din_tag <= 0; + din_cont <= 0; + din_qspi <= 0; + din_ddr <= 0; + din_rd <= 0; + end else begin + if (dout_valid && dout_tag == 1) buffer[ 7: 0] <= dout_data; + if (dout_valid && dout_tag == 2) buffer[15: 8] <= dout_data; + if (dout_valid && dout_tag == 3) buffer[23:16] <= dout_data; + if (dout_valid && dout_tag == 4) begin + rdata <= {dout_data, buffer}; + rd_addr <= rd_inc ? rd_addr + 4 : addr; + rd_valid <= 1; + rd_wait <= rd_inc; + rd_inc <= 1; + end + + if (valid) + rd_wait <= 0; + + case (state) + 0: begin + din_valid <= 1; + din_data <= 8'h ff; + din_tag <= 0; + if (din_ready) begin + din_valid <= 0; + state <= 1; + end + end + 1: begin + if (dout_valid) begin + xfer_resetn <= 0; + state <= 2; + end + end + 2: begin + din_valid <= 1; + din_data <= 8'h ab; + din_tag <= 0; + if (din_ready) begin + din_valid <= 0; + state <= 3; + end + end + 3: begin + if (dout_valid) begin + xfer_resetn <= 0; + state <= 4; + end + end + 4: begin + rd_inc <= 0; + din_valid <= 1; + din_tag <= 0; + case ({config_ddr, config_qspi}) + 2'b11: din_data <= 8'h ED; + 2'b01: din_data <= 8'h EB; + 2'b10: din_data <= 8'h BB; + 2'b00: din_data <= 8'h 03; + endcase + if (din_ready) begin + din_valid <= 0; + state <= 5; + end + end + 5: begin + if (valid && !ready) begin + din_valid <= 1; + din_tag <= 0; + din_data <= addr[23:16]; + din_qspi <= config_qspi; + din_ddr <= config_ddr; + if (din_ready) begin + din_valid <= 0; + state <= 6; + end + end + end + 6: begin + din_valid <= 1; + din_tag <= 0; + din_data <= addr[15:8]; + if (din_ready) begin + din_valid <= 0; + state <= 7; + end + end + 7: begin + din_valid <= 1; + din_tag <= 0; + din_data <= addr[7:0]; + if (din_ready) begin + din_valid <= 0; + din_data <= 0; + state <= config_qspi || config_ddr ? 8 : 9; + end + end + 8: begin + din_valid <= 1; + din_tag <= 0; + din_data <= config_cont ? 8'h A5 : 8'h FF; + if (din_ready) begin + din_rd <= 1; + din_data <= config_dummy; + din_valid <= 0; + state <= 9; + end + end + 9: begin + din_valid <= 1; + din_tag <= 1; + if (din_ready) begin + din_valid <= 0; + state <= 10; + end + end + 10: begin + din_valid <= 1; + din_data <= 8'h 00; + din_tag <= 2; + if (din_ready) begin + din_valid <= 0; + state <= 11; + end + end + 11: begin + din_valid <= 1; + din_tag <= 3; + if (din_ready) begin + din_valid <= 0; + state <= 12; + end + end + 12: begin + if (!rd_wait || valid) begin + din_valid <= 1; + din_tag <= 4; + if (din_ready) begin + din_valid <= 0; + state <= 9; + end + end + end + endcase + + if (jump) begin + rd_inc <= 0; + rd_valid <= 0; + xfer_resetn <= 0; + if (config_cont) begin + state <= 5; + end else begin + state <= 4; + din_qspi <= 0; + din_ddr <= 0; + end + din_rd <= 0; + end + end + end +endmodule + +module spimemio_xfer ( + input clk, resetn, + + input din_valid, + output din_ready, + input [7:0] din_data, + input [3:0] din_tag, + input din_cont, + input din_dspi, + input din_qspi, + input din_ddr, + input din_rd, + + output dout_valid, + output [7:0] dout_data, + output [3:0] dout_tag, + + output reg flash_csb, + output reg flash_clk, + + output reg flash_io0_oe, + output reg flash_io1_oe, + output reg flash_io2_oe, + output reg flash_io3_oe, + + output reg flash_io0_do, + output reg flash_io1_do, + output reg flash_io2_do, + output reg flash_io3_do, + + input flash_io0_di, + input flash_io1_di, + input flash_io2_di, + input flash_io3_di +); + reg [7:0] obuffer; + reg [7:0] ibuffer; + + reg [3:0] count; + reg [3:0] dummy_count; + + reg xfer_cont; + reg xfer_dspi; + reg xfer_qspi; + reg xfer_ddr; + reg xfer_ddr_q; + reg xfer_rd; + reg [3:0] xfer_tag; + reg [3:0] xfer_tag_q; + + reg [7:0] next_obuffer; + reg [7:0] next_ibuffer; + reg [3:0] next_count; + + reg fetch; + reg next_fetch; + reg last_fetch; + + always @(posedge clk) begin + xfer_ddr_q <= xfer_ddr; + xfer_tag_q <= xfer_tag; + end + + assign din_ready = din_valid && resetn && next_fetch; + + assign dout_valid = (xfer_ddr_q ? fetch && !last_fetch : next_fetch && !fetch) && resetn; + assign dout_data = ibuffer; + assign dout_tag = xfer_tag_q; + + always @* begin + flash_io0_oe = 0; + flash_io1_oe = 0; + flash_io2_oe = 0; + flash_io3_oe = 0; + + flash_io0_do = 0; + flash_io1_do = 0; + flash_io2_do = 0; + flash_io3_do = 0; + + next_obuffer = obuffer; + next_ibuffer = ibuffer; + next_count = count; + next_fetch = 0; + + if (dummy_count == 0) begin + casez ({xfer_ddr, xfer_qspi, xfer_dspi}) + 3'b 000: begin + flash_io0_oe = 1; + flash_io0_do = obuffer[7]; + + if (flash_clk) begin + next_obuffer = {obuffer[6:0], 1'b 0}; + next_count = count - |count; + end else begin + next_ibuffer = {ibuffer[6:0], flash_io1_di}; + end + + next_fetch = (next_count == 0); + end + 3'b 01?: begin + flash_io0_oe = !xfer_rd; + flash_io1_oe = !xfer_rd; + flash_io2_oe = !xfer_rd; + flash_io3_oe = !xfer_rd; + + flash_io0_do = obuffer[4]; + flash_io1_do = obuffer[5]; + flash_io2_do = obuffer[6]; + flash_io3_do = obuffer[7]; + + if (flash_clk) begin + next_obuffer = {obuffer[3:0], 4'b 0000}; + next_count = count - {|count, 2'b00}; + end else begin + next_ibuffer = {ibuffer[3:0], flash_io3_di, flash_io2_di, flash_io1_di, flash_io0_di}; + end + + next_fetch = (next_count == 0); + end + 3'b 11?: begin + flash_io0_oe = !xfer_rd; + flash_io1_oe = !xfer_rd; + flash_io2_oe = !xfer_rd; + flash_io3_oe = !xfer_rd; + + flash_io0_do = obuffer[4]; + flash_io1_do = obuffer[5]; + flash_io2_do = obuffer[6]; + flash_io3_do = obuffer[7]; + + next_obuffer = {obuffer[3:0], 4'b 0000}; + next_ibuffer = {ibuffer[3:0], flash_io3_di, flash_io2_di, flash_io1_di, flash_io0_di}; + next_count = count - {|count, 2'b00}; + + next_fetch = (next_count == 0); + end + 3'b ??1: begin + flash_io0_oe = !xfer_rd; + flash_io1_oe = !xfer_rd; + + flash_io0_do = obuffer[6]; + flash_io1_do = obuffer[7]; + + if (flash_clk) begin + next_obuffer = {obuffer[5:0], 2'b 00}; + next_count = count - {|count, 1'b0}; + end else begin + next_ibuffer = {ibuffer[5:0], flash_io1_di, flash_io0_di}; + end + + next_fetch = (next_count == 0); + end + endcase + end + end + + always @(posedge clk) begin + if (!resetn) begin + fetch <= 1; + last_fetch <= 1; + flash_csb <= 1; + flash_clk <= 0; + count <= 0; + dummy_count <= 0; + xfer_tag <= 0; + xfer_cont <= 0; + xfer_dspi <= 0; + xfer_qspi <= 0; + xfer_ddr <= 0; + xfer_rd <= 0; + end else begin + fetch <= next_fetch; + last_fetch <= xfer_ddr ? fetch : 1; + if (dummy_count) begin + flash_clk <= !flash_clk && !flash_csb; + dummy_count <= dummy_count - flash_clk; + end else + if (count) begin + flash_clk <= !flash_clk && !flash_csb; + obuffer <= next_obuffer; + ibuffer <= next_ibuffer; + count <= next_count; + end + if (din_valid && din_ready) begin + flash_csb <= 0; + flash_clk <= 0; + + count <= 8; + dummy_count <= din_rd ? din_data : 0; + obuffer <= din_data; + + xfer_tag <= din_tag; + xfer_cont <= din_cont; + xfer_dspi <= din_dspi; + xfer_qspi <= din_qspi; + xfer_ddr <= din_ddr; + xfer_rd <= din_rd; + end + end + end +endmodule diff --git a/workshop.py b/workshop.py new file mode 100644 index 0000000..81c35aa --- /dev/null +++ b/workshop.py @@ -0,0 +1,330 @@ +#!/usr/bin/env python3 +# This variable defines all the external programs that this module +# relies on. lxbuildenv reads this variable in order to ensure +# the build will finish without exiting due to missing third-party +# programs. +LX_DEPENDENCIES = ["riscv", "icestorm"] + +# Import lxbuildenv to integrate the deps/ directory +import lxbuildenv + # "python.autoComplete.extraPaths": [ + # "deps/litescope", + # "deps/litex", + # "deps/litex_boards", + # "deps/lxsocsupport", + # "deps/migen", + # "deps/valentyusb" + # ] + +# Disable pylint's E1101, which breaks completely on migen +#pylint:disable=E1101 + +from migen import Module, Signal, Instance, ClockDomain, If +from migen.genlib.resetsync import AsyncResetSynchronizer +from migen.fhdl.specials import TSTriple +from migen.fhdl.bitcontainer import bits_for +from migen.fhdl.structure import ClockSignal, ResetSignal, Replicate, Cat + +from litex_boards.partner.platforms.fomu_evt import Platform +from litex.soc.integration import SoCCore +from litex.soc.integration.builder import Builder +from litex.soc.integration.soc_core import csr_map_update +from litex.soc.interconnect import wishbone +from litex.soc.interconnect.csr import AutoCSR, CSRStatus, CSRStorage +from lxsocsupport import up5kspram + +class _CRG(Module): + def __init__(self, platform, use_pll): + clk48_raw = platform.request("clk48") + clk12_raw = Signal() + clk48 = Signal() + clk12 = Signal() + + reset_delay = Signal(13, reset=4095) + self.clock_domains.cd_por = ClockDomain() + self.reset = Signal() + + self.clock_domains.cd_sys = ClockDomain() + self.clock_domains.cd_usb_12 = ClockDomain() + self.clock_domains.cd_usb_48 = ClockDomain() + + platform.add_period_constraint(self.cd_usb_48.clk, 1e9/48e6) + platform.add_period_constraint(self.cd_sys.clk, 1e9/12e6) + platform.add_period_constraint(self.cd_usb_12.clk, 1e9/12e6) + platform.add_period_constraint(clk48, 1e9/48e6) + platform.add_period_constraint(clk48_raw, 1e9/48e6) + platform.add_period_constraint(clk12_raw, 1e9/12e6) + + # POR reset logic- POR generated from sys clk, POR logic feeds sys clk + # reset. + self.comb += [ + self.cd_por.clk.eq(self.cd_sys.clk), + self.cd_sys.rst.eq(reset_delay != 0), + self.cd_usb_12.rst.eq(reset_delay != 0), + ] + + if use_pll: + + # Divide clk48 down to clk12, to ensure they're synchronized. + # By doing this, we avoid needing clock-domain crossing. + clk12_counter = Signal(2) + + self.clock_domains.cd_usb_48_raw = ClockDomain() + + platform.add_period_constraint(self.cd_usb_48_raw.clk, 1e9/48e6) + + # POR reset logic- POR generated from sys clk, POR logic feeds sys clk + # reset. + self.comb += [ + self.cd_usb_48.rst.eq(reset_delay != 0), + ] + + self.comb += self.cd_usb_48_raw.clk.eq(clk48_raw) + self.comb += self.cd_usb_48.clk.eq(clk48) + + self.sync.usb_48_raw += clk12_counter.eq(clk12_counter + 1) + + self.comb += clk12_raw.eq(clk12_counter[1]) + self.specials += Instance( + "SB_GB", + i_USER_SIGNAL_TO_GLOBAL_BUFFER=clk12_raw, + o_GLOBAL_BUFFER_OUTPUT=clk12, + ) + + self.specials += Instance( + "SB_PLL40_CORE", + # Parameters + p_DIVR = 0, + p_DIVF = 3, + p_DIVQ = 2, + p_FILTER_RANGE = 1, + p_FEEDBACK_PATH = "PHASE_AND_DELAY", + p_DELAY_ADJUSTMENT_MODE_FEEDBACK = "FIXED", + p_FDA_FEEDBACK = 15, + p_DELAY_ADJUSTMENT_MODE_RELATIVE = "FIXED", + p_FDA_RELATIVE = 0, + p_SHIFTREG_DIV_MODE = 1, + p_PLLOUT_SELECT = "SHIFTREG_0deg", + p_ENABLE_ICEGATE = 0, + # IO + i_REFERENCECLK = clk12, + o_PLLOUTGLOBAL = clk48, + i_BYPASS = 0, + i_RESETB = 1, + ) + else: + self.specials += Instance( + "SB_GB", + i_USER_SIGNAL_TO_GLOBAL_BUFFER=clk48_raw, + o_GLOBAL_BUFFER_OUTPUT=clk48, + ) + self.comb += self.cd_usb_48.clk.eq(clk48) + + clk12_counter = Signal(2) + self.sync.usb_48 += clk12_counter.eq(clk12_counter + 1) + + self.comb += clk12_raw.eq(clk12_counter[1]) + self.specials += Instance( + "SB_GB", + i_USER_SIGNAL_TO_GLOBAL_BUFFER=clk12_raw, + o_GLOBAL_BUFFER_OUTPUT=clk12, + ) + + self.comb += self.cd_sys.clk.eq(clk12) + self.comb += self.cd_usb_12.clk.eq(clk12) + + self.sync.por += \ + If(reset_delay != 0, + reset_delay.eq(reset_delay - 1) + ) + self.specials += AsyncResetSynchronizer(self.cd_por, self.reset) + +class PicoRVSpi(Module, AutoCSR): + def __init__(self, platform, pads, size=2*1024*1024): + self.size = size + + self.bus = bus = wishbone.Interface() + + self.reset = Signal() + + self.cfg1 = CSRStorage(size=8) + self.cfg2 = CSRStorage(size=8) + self.cfg3 = CSRStorage(size=8) + self.cfg4 = CSRStorage(size=8) + + self.stat1 = CSRStatus(size=8) + self.stat2 = CSRStatus(size=8) + self.stat3 = CSRStatus(size=8) + self.stat4 = CSRStatus(size=8) + + cfg = Signal(32) + cfg_we = Signal(4) + cfg_out = Signal(32) + self.comb += [ + cfg.eq(Cat(self.cfg1.storage, self.cfg2.storage, self.cfg3.storage, self.cfg4.storage)), + cfg_we.eq(Cat(self.cfg1.re, self.cfg2.re, self.cfg3.re, self.cfg4.re)), + self.stat1.status.eq(cfg_out[0:8]), + self.stat2.status.eq(cfg_out[8:16]), + self.stat3.status.eq(cfg_out[16:24]), + self.stat4.status.eq(cfg_out[24:32]), + ] + + mosi_pad = TSTriple() + miso_pad = TSTriple() + cs_n_pad = TSTriple() + clk_pad = TSTriple() + wp_pad = TSTriple() + hold_pad = TSTriple() + self.specials += mosi_pad.get_tristate(pads.mosi) + self.specials += miso_pad.get_tristate(pads.miso) + self.specials += cs_n_pad.get_tristate(pads.cs_n) + self.specials += clk_pad.get_tristate(pads.clk) + self.specials += wp_pad.get_tristate(pads.wp) + self.specials += hold_pad.get_tristate(pads.hold) + + reset = Signal() + self.comb += [ + reset.eq(ResetSignal() | self.reset), + cs_n_pad.oe.eq(~reset), + clk_pad.oe.eq(~reset), + ] + + flash_addr = Signal(24) + mem_bits = bits_for(size) + self.comb += flash_addr.eq(bus.adr[0:mem_bits-2] << 2), + + read_active = Signal() + spi_ready = Signal() + self.sync += [ + If(bus.stb & bus.cyc & ~read_active, + read_active.eq(1), + bus.ack.eq(0), + ) + .Elif(read_active & spi_ready, + read_active.eq(0), + bus.ack.eq(1), + ) + .Else( + bus.ack.eq(0), + read_active.eq(0), + ) + ] + + o_rdata = Signal(32) + self.comb += bus.dat_r.eq(o_rdata) + + self.specials += Instance("spimemio", + o_flash_io0_oe = mosi_pad.oe, + o_flash_io1_oe = miso_pad.oe, + o_flash_io2_oe = wp_pad.oe, + o_flash_io3_oe = hold_pad.oe, + + o_flash_io0_do = mosi_pad.o, + o_flash_io1_do = miso_pad.o, + o_flash_io2_do = wp_pad.o, + o_flash_io3_do = hold_pad.o, + o_flash_csb = cs_n_pad.o, + o_flash_clk = clk_pad.o, + + i_flash_io0_di = mosi_pad.i, + i_flash_io1_di = miso_pad.i, + i_flash_io2_di = wp_pad.i, + i_flash_io3_di = hold_pad.i, + + i_resetn = ~reset, + i_clk = ClockSignal(), + + i_valid = bus.stb & bus.cyc, + o_ready = spi_ready, + i_addr = flash_addr, + o_rdata = o_rdata, + + i_cfgreg_we = cfg_we, + i_cfgreg_di = cfg, + o_cfgreg_do = cfg_out, + ) + platform.add_source("rtl/spimemio.v") + +class BaseSoC(SoCCore): + csr_peripherals = [ + "ddrphy", +# "dna", + "xadc", + "cpu_or_bridge", + ] + SoCCore.csr_map = { + "ctrl": 0, # provided by default (optional) + "crg": 1, # user + "uart_phy": 2, # provided by default (optional) + "uart": 3, # provided by default (optional) + "identifier_mem": 4, # provided by default (optional) + "timer0": 5, # provided by default (optional) + "cpu_or_bridge": 8, + "usb": 9, + "picorvspi": 10, + "touch": 11, + "reboot": 12, + "rgb": 13, + "version": 14, + } + + mem_map = { + "spiflash": 0x20000000, # (default shadow @0xa0000000) + } + mem_map.update(SoCCore.mem_map) + + def __init__(self, platform, output_dir="build", use_pll=True, **kwargs): + clk_freq = int(12e6) + self.output_dir = output_dir + self.submodules.crg = _CRG(platform, use_pll=use_pll) + SoCCore.__init__(self, platform, clk_freq, + integrated_sram_size=0, with_uart=False, + **kwargs) + + # SPRAM- UP5K has single port RAM, might as well use it as SRAM to + # free up scarce block RAM. + spram_size = 128*1024 + self.submodules.spram = up5kspram.Up5kSPRAM(size=spram_size) + self.register_mem("sram", 0x10000000, self.spram.bus, spram_size) + + # Add a simple bit-banged SPI Flash module based on PicoRVSpi + spi_pads = platform.request("spiflash") + self.submodules.picorvspi = PicoRVSpi(platform, spi_pads) + self.register_mem("spiflash", self.mem_map["spiflash"], + self.picorvspi.bus, size=self.picorvspi.size) + + bios_size = 0x8000 + kwargs['cpu_reset_address']=self.mem_map["spiflash"]+platform.gateware_size + self.add_memory_region("rom", kwargs['cpu_reset_address'], bios_size) + self.add_constant("ROM_DISABLE", 1) + self.flash_boot_address = self.mem_map["spiflash"]+platform.gateware_size+bios_size + self.add_memory_region("user_flash", + self.flash_boot_address, + # Leave a grace area- possible one-by-off bug in add_memory_region? + # Possible fix: addr < origin + length - 1 + platform.spiflash_total_size - (self.flash_boot_address - self.mem_map["spiflash"]) - 0x100) + + if hasattr(self, "cpu"): + self.cpu.use_external_variant("rtl/2-stage-1024-cache.v") + self.copy_memory_file("2-stage-1024-cache.v_toplevel_RegFilePlugin_regFile.bin") + + def copy_memory_file(self, src): + import os + from shutil import copyfile + if not os.path.exists(self.output_dir): + os.mkdir(self.output_dir) + if not os.path.exists(os.path.join(self.output_dir, "gateware")): + os.mkdir(os.path.join(self.output_dir, "gateware")) + copyfile(os.path.join("rtl", src), os.path.join(self.output_dir, "gateware", src)) + +def main(): + platform = Platform() + soc = BaseSoC(platform) + builder = Builder(soc, + output_dir="build", csr_csv="test/csr.csv", + compile_software=False) + vns = builder.build() + soc.do_exit(vns) + +if __name__ == "__main__": + main()