Merge branch 'master' of github.com:im-tomu/fomu-workshop

README.md

@@ -679,7 +679,7 @@ Migen is an HDL embedded in Python, and LiteX provides us with a Wishbone abstra
 
 We can use `DummyUsb` to respond to USB requests and bridge USB to Wishbone, and rely on LiteX to generate registers and wire them to hardware signals.  We can still use `wishbone-tool` to read and write memory, and with a wishbone bridge we can actually have code running on our local system that can read and write memory on Fomu.
 
-Go to the `litex` directory and build the design and load it onto Fomu:
+Go to the `litex` directory and build the design;
 
 ```sh
 $ python3 workshop.py --board hacker
@@ -714,16 +714,17 @@ Info: [ 67539,  71542) |*************+
 Info: [ 71542,  75545) |********************+
 Info: [ 75545,  79548) |************************************************************
 5 warnings, 0 errors
-$ dfu-util -D build/gateware/top.bin
+```
+
+Load it onto Fomu:
+```sh
+$ dfu-util -D build/gateware/top.dfu
 dfu-util 0.8
 Copyright 2005-2009 Weston Schmidt, Harald Welte and OpenMoko Inc.
 Copyright 2010-2014 Tormod Volden and Stefan Schmidt
 This program is Free Software and has ABSOLUTELY NO WARRANTY
 Please report bugs to dfu-util@lists.gnumonks.org
 
-Invalid DFU suffix signature
-A valid DFU suffix will be required in a future dfu-util release!!!
-Cannot open DFU device 0b05:180a
 Opening DFU capable USB device...
 ID 1209:5bf0
 Run-time device DFU version 0101

litex/workshop.py

@@ -7,7 +7,7 @@ LX_DEPENDENCIES = ["icestorm", "yosys", "nextpnr-ice40"]
 LX_CONFIG = "skip-git"
 
 # Import lxbuildenv to integrate the deps/ directory
-import os,sys
+import os,os.path,shutil,sys,subprocess
 sys.path.insert(0, os.path.dirname(__file__))
 import lxbuildenv
 
@@ -86,6 +86,14 @@ class BaseSoC(SoCCore):
         if placer is not None:
             platform.toolchain.nextpnr_build_template[1] += " --placer {}".format(placer)
 
+
+def add_dfu_suffix(fn):
+    fn_base, ext = os.path.splitext(fn)
+    fn_dfu = fn_base + '.dfu'
+    shutil.copyfile(fn, fn_dfu)
+    subprocess.check_call(['dfu-suffix', '--pid', '1209', '--vid', '5bf0', '--add', fn_dfu])
+
+
 def main():
     parser = argparse.ArgumentParser(
         description="Build Fomu Main Gateware")
@@ -117,6 +125,8 @@ def main():
                       compile_software=False)
     vns = builder.build()
     soc.do_exit(vns)
+    add_dfu_suffix(os.path.join('build', 'gateware', 'top.bin'))
+
 
 if __name__ == "__main__":
     main()

verilog-blink-minimal/README.md

@@ -2,8 +2,13 @@
 
 A more minimal Verilog example.
 
-
 Unlike the example in ../verilog-blink it;
  - **only** works on the **Fomu hacker board**.
  - **only** works on Linux
  - doesn't use any Makefile variables.
+
+## Using
+
+ Type `make` to build the DFU image.
+ Type `make load` to load the DFU image onto the Fomu board.
+ Type `make clean` to remove all the generated files.