330 lines
11 KiB
Python
330 lines
11 KiB
Python
#!/usr/bin/env python3
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# This variable defines all the external programs that this module
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# relies on. lxbuildenv reads this variable in order to ensure
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# the build will finish without exiting due to missing third-party
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# programs.
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LX_DEPENDENCIES = ["riscv", "icestorm"]
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# Import lxbuildenv to integrate the deps/ directory
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import lxbuildenv
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# "python.autoComplete.extraPaths": [
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# "deps/litescope",
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# "deps/litex",
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# "deps/litex_boards",
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# "deps/lxsocsupport",
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# "deps/migen",
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# "deps/valentyusb"
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# ]
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# Disable pylint's E1101, which breaks completely on migen
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#pylint:disable=E1101
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from migen import Module, Signal, Instance, ClockDomain, If
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from migen.fhdl.specials import TSTriple
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from migen.fhdl.bitcontainer import bits_for
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from migen.fhdl.structure import ClockSignal, ResetSignal, Replicate, Cat
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from litex_boards.partner.platforms.fomu_evt import Platform
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from litex.soc.integration import SoCCore
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from litex.soc.integration.builder import Builder
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from litex.soc.integration.soc_core import csr_map_update
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from litex.soc.interconnect import wishbone
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from litex.soc.interconnect.csr import AutoCSR, CSRStatus, CSRStorage
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from lxsocsupport import up5kspram
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class _CRG(Module):
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def __init__(self, platform, use_pll):
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clk48_raw = platform.request("clk48")
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clk12_raw = Signal()
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clk48 = Signal()
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clk12 = Signal()
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reset_delay = Signal(13, reset=4095)
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self.clock_domains.cd_por = ClockDomain()
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self.reset = Signal()
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_usb_12 = ClockDomain()
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self.clock_domains.cd_usb_48 = ClockDomain()
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platform.add_period_constraint(self.cd_usb_48.clk, 1e9/48e6)
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platform.add_period_constraint(self.cd_sys.clk, 1e9/12e6)
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platform.add_period_constraint(self.cd_usb_12.clk, 1e9/12e6)
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platform.add_period_constraint(clk48, 1e9/48e6)
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platform.add_period_constraint(clk48_raw, 1e9/48e6)
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platform.add_period_constraint(clk12_raw, 1e9/12e6)
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# POR reset logic- POR generated from sys clk, POR logic feeds sys clk
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# reset.
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self.comb += [
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self.cd_por.clk.eq(self.cd_sys.clk),
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self.cd_sys.rst.eq(reset_delay != 0),
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self.cd_usb_12.rst.eq(reset_delay != 0),
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]
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if use_pll:
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# Divide clk48 down to clk12, to ensure they're synchronized.
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# By doing this, we avoid needing clock-domain crossing.
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clk12_counter = Signal(2)
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self.clock_domains.cd_usb_48_raw = ClockDomain()
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platform.add_period_constraint(self.cd_usb_48_raw.clk, 1e9/48e6)
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# POR reset logic- POR generated from sys clk, POR logic feeds sys clk
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# reset.
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self.comb += [
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self.cd_usb_48.rst.eq(reset_delay != 0),
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]
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self.comb += self.cd_usb_48_raw.clk.eq(clk48_raw)
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self.comb += self.cd_usb_48.clk.eq(clk48)
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self.sync.usb_48_raw += clk12_counter.eq(clk12_counter + 1)
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self.comb += clk12_raw.eq(clk12_counter[1])
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self.specials += Instance(
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"SB_GB",
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i_USER_SIGNAL_TO_GLOBAL_BUFFER=clk12_raw,
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o_GLOBAL_BUFFER_OUTPUT=clk12,
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)
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self.specials += Instance(
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"SB_PLL40_CORE",
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# Parameters
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p_DIVR = 0,
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p_DIVF = 3,
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p_DIVQ = 2,
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p_FILTER_RANGE = 1,
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p_FEEDBACK_PATH = "PHASE_AND_DELAY",
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p_DELAY_ADJUSTMENT_MODE_FEEDBACK = "FIXED",
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p_FDA_FEEDBACK = 15,
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p_DELAY_ADJUSTMENT_MODE_RELATIVE = "FIXED",
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p_FDA_RELATIVE = 0,
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p_SHIFTREG_DIV_MODE = 1,
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p_PLLOUT_SELECT = "SHIFTREG_0deg",
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p_ENABLE_ICEGATE = 0,
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# IO
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i_REFERENCECLK = clk12,
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o_PLLOUTGLOBAL = clk48,
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i_BYPASS = 0,
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i_RESETB = 1,
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)
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else:
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self.specials += Instance(
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"SB_GB",
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i_USER_SIGNAL_TO_GLOBAL_BUFFER=clk48_raw,
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o_GLOBAL_BUFFER_OUTPUT=clk48,
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)
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self.comb += self.cd_usb_48.clk.eq(clk48)
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clk12_counter = Signal(2)
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self.sync.usb_48 += clk12_counter.eq(clk12_counter + 1)
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self.comb += clk12_raw.eq(clk12_counter[1])
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self.specials += Instance(
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"SB_GB",
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i_USER_SIGNAL_TO_GLOBAL_BUFFER=clk12_raw,
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o_GLOBAL_BUFFER_OUTPUT=clk12,
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)
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self.comb += self.cd_sys.clk.eq(clk12)
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self.comb += self.cd_usb_12.clk.eq(clk12)
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self.sync.por += \
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If(reset_delay != 0,
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reset_delay.eq(reset_delay - 1)
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)
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self.specials += AsyncResetSynchronizer(self.cd_por, self.reset)
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class PicoRVSpi(Module, AutoCSR):
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def __init__(self, platform, pads, size=2*1024*1024):
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self.size = size
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self.bus = bus = wishbone.Interface()
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self.reset = Signal()
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self.cfg1 = CSRStorage(size=8)
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self.cfg2 = CSRStorage(size=8)
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self.cfg3 = CSRStorage(size=8)
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self.cfg4 = CSRStorage(size=8)
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self.stat1 = CSRStatus(size=8)
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self.stat2 = CSRStatus(size=8)
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self.stat3 = CSRStatus(size=8)
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self.stat4 = CSRStatus(size=8)
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cfg = Signal(32)
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cfg_we = Signal(4)
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cfg_out = Signal(32)
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self.comb += [
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cfg.eq(Cat(self.cfg1.storage, self.cfg2.storage, self.cfg3.storage, self.cfg4.storage)),
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cfg_we.eq(Cat(self.cfg1.re, self.cfg2.re, self.cfg3.re, self.cfg4.re)),
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self.stat1.status.eq(cfg_out[0:8]),
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self.stat2.status.eq(cfg_out[8:16]),
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self.stat3.status.eq(cfg_out[16:24]),
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self.stat4.status.eq(cfg_out[24:32]),
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]
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mosi_pad = TSTriple()
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miso_pad = TSTriple()
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cs_n_pad = TSTriple()
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clk_pad = TSTriple()
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wp_pad = TSTriple()
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hold_pad = TSTriple()
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self.specials += mosi_pad.get_tristate(pads.mosi)
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self.specials += miso_pad.get_tristate(pads.miso)
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self.specials += cs_n_pad.get_tristate(pads.cs_n)
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self.specials += clk_pad.get_tristate(pads.clk)
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self.specials += wp_pad.get_tristate(pads.wp)
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self.specials += hold_pad.get_tristate(pads.hold)
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reset = Signal()
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self.comb += [
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reset.eq(ResetSignal() | self.reset),
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cs_n_pad.oe.eq(~reset),
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clk_pad.oe.eq(~reset),
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]
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flash_addr = Signal(24)
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mem_bits = bits_for(size)
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self.comb += flash_addr.eq(bus.adr[0:mem_bits-2] << 2),
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read_active = Signal()
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spi_ready = Signal()
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self.sync += [
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If(bus.stb & bus.cyc & ~read_active,
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read_active.eq(1),
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bus.ack.eq(0),
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)
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.Elif(read_active & spi_ready,
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read_active.eq(0),
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bus.ack.eq(1),
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)
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.Else(
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bus.ack.eq(0),
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read_active.eq(0),
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)
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]
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o_rdata = Signal(32)
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self.comb += bus.dat_r.eq(o_rdata)
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self.specials += Instance("spimemio",
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o_flash_io0_oe = mosi_pad.oe,
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o_flash_io1_oe = miso_pad.oe,
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o_flash_io2_oe = wp_pad.oe,
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o_flash_io3_oe = hold_pad.oe,
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o_flash_io0_do = mosi_pad.o,
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o_flash_io1_do = miso_pad.o,
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o_flash_io2_do = wp_pad.o,
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o_flash_io3_do = hold_pad.o,
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o_flash_csb = cs_n_pad.o,
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o_flash_clk = clk_pad.o,
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i_flash_io0_di = mosi_pad.i,
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i_flash_io1_di = miso_pad.i,
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i_flash_io2_di = wp_pad.i,
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i_flash_io3_di = hold_pad.i,
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i_resetn = ~reset,
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i_clk = ClockSignal(),
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i_valid = bus.stb & bus.cyc,
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o_ready = spi_ready,
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i_addr = flash_addr,
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o_rdata = o_rdata,
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i_cfgreg_we = cfg_we,
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i_cfgreg_di = cfg,
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o_cfgreg_do = cfg_out,
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)
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platform.add_source("rtl/spimemio.v")
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class BaseSoC(SoCCore):
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csr_peripherals = [
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"ddrphy",
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# "dna",
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"xadc",
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"cpu_or_bridge",
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]
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SoCCore.csr_map = {
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"ctrl": 0, # provided by default (optional)
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"crg": 1, # user
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"uart_phy": 2, # provided by default (optional)
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"uart": 3, # provided by default (optional)
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"identifier_mem": 4, # provided by default (optional)
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"timer0": 5, # provided by default (optional)
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"cpu_or_bridge": 8,
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"usb": 9,
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"picorvspi": 10,
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"touch": 11,
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"reboot": 12,
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"rgb": 13,
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"version": 14,
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}
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mem_map = {
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"spiflash": 0x20000000, # (default shadow @0xa0000000)
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}
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mem_map.update(SoCCore.mem_map)
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def __init__(self, platform, output_dir="build", use_pll=True, **kwargs):
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clk_freq = int(12e6)
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self.output_dir = output_dir
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self.submodules.crg = _CRG(platform, use_pll=use_pll)
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SoCCore.__init__(self, platform, clk_freq,
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integrated_sram_size=0, with_uart=False,
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**kwargs)
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# SPRAM- UP5K has single port RAM, might as well use it as SRAM to
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# free up scarce block RAM.
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spram_size = 128*1024
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self.submodules.spram = up5kspram.Up5kSPRAM(size=spram_size)
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self.register_mem("sram", 0x10000000, self.spram.bus, spram_size)
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# Add a simple bit-banged SPI Flash module based on PicoRVSpi
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spi_pads = platform.request("spiflash")
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self.submodules.picorvspi = PicoRVSpi(platform, spi_pads)
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self.register_mem("spiflash", self.mem_map["spiflash"],
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self.picorvspi.bus, size=self.picorvspi.size)
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bios_size = 0x8000
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kwargs['cpu_reset_address']=self.mem_map["spiflash"]+platform.gateware_size
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self.add_memory_region("rom", kwargs['cpu_reset_address'], bios_size)
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self.add_constant("ROM_DISABLE", 1)
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self.flash_boot_address = self.mem_map["spiflash"]+platform.gateware_size+bios_size
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self.add_memory_region("user_flash",
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self.flash_boot_address,
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# Leave a grace area- possible one-by-off bug in add_memory_region?
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# Possible fix: addr < origin + length - 1
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platform.spiflash_total_size - (self.flash_boot_address - self.mem_map["spiflash"]) - 0x100)
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if hasattr(self, "cpu"):
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self.cpu.use_external_variant("rtl/2-stage-1024-cache.v")
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self.copy_memory_file("2-stage-1024-cache.v_toplevel_RegFilePlugin_regFile.bin")
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def copy_memory_file(self, src):
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import os
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from shutil import copyfile
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if not os.path.exists(self.output_dir):
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os.mkdir(self.output_dir)
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if not os.path.exists(os.path.join(self.output_dir, "gateware")):
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os.mkdir(os.path.join(self.output_dir, "gateware"))
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copyfile(os.path.join("rtl", src), os.path.join(self.output_dir, "gateware", src))
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def main():
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platform = Platform()
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soc = BaseSoC(platform)
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builder = Builder(soc,
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output_dir="build", csr_csv="test/csr.csv",
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compile_software=False)
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vns = builder.build()
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soc.do_exit(vns)
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if __name__ == "__main__":
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main()
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