From 02f1d705b74c4d207e1a4c1703310094a380329a Mon Sep 17 00:00:00 2001
From: Graham Edgecombe <gpe@grahamedgecombe.com>
Date: Sun, 3 Dec 2017 21:03:19 +0000
Subject: [PATCH] Reset {rs1,rs2_out} when flushing the decode stage

This will prevent us needing to stall the pipeline for a load
instruction if the rs1/rs2 registers happened to match the rd register.
---
 rv32_decode.sv | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/rv32_decode.sv b/rv32_decode.sv
index c0fab65..8bffbee 100644
--- a/rv32_decode.sv
+++ b/rv32_decode.sv
@@ -487,6 +487,8 @@ module rv32_decode (
             endcase
 
             if (flush) begin
+                rs1_out <= 0;
+                rs2_out <= 0;
                 mem_read_en_out <= 0;
                 mem_write_en_out <= 0;
                 branch_op_out <= RV32_BRANCH_OP_NEVER;