From 08c4451abf838b861ffa450965ca1f06a71d64e5 Mon Sep 17 00:00:00 2001
From: Graham Edgecombe <gpe@grahamedgecombe.com>
Date: Sat, 2 Dec 2017 20:26:56 +0000
Subject: [PATCH] Add clock divider

---
 clk_div.sv | 18 ++++++++++++++++++
 top.sv     | 12 +++++++++++-
 2 files changed, 29 insertions(+), 1 deletion(-)
 create mode 100644 clk_div.sv

diff --git a/clk_div.sv b/clk_div.sv
new file mode 100644
index 0000000..16860f9
--- /dev/null
+++ b/clk_div.sv
@@ -0,0 +1,18 @@
+`ifndef CLK_DIV
+`define CLK_DIV
+
+module clk_div #(
+    parameter LOG_DIVISOR = 1
+) (
+    input clk_in,
+    output clk_out
+);
+    wire [LOG_DIVISOR-1:0] q;
+
+    always_ff @(posedge clk_in)
+        q <= q + 1;
+
+    assign clk_out = q[LOG_DIVISOR-1];
+endmodule
+
+`endif
diff --git a/top.sv b/top.sv
index e7871c9..e1d9e04 100644
--- a/top.sv
+++ b/top.sv
@@ -1,3 +1,4 @@
+`include "clk_div.sv"
 `include "rv32.sv"
 
 module top (
@@ -33,8 +34,17 @@ module top (
         .D_OUT_0({flash_io1_out, flash_io0_out})
     );
 
+    logic clk_slow;
+
+    clk_div #(
+        .LOG_DIVISOR(18)
+    ) clk_div (
+        .clk_in(clk),
+        .clk_out(clk_slow)
+    );
+
     rv32 rv32 (
-        .clk(clk),
+        .clk(clk_slow),
         .leds(leds)
     );
 endmodule