diff --git a/rv32.sv b/rv32.sv index 670d964..45ba0d5 100644 --- a/rv32.sv +++ b/rv32.sv @@ -18,17 +18,18 @@ module rv32 ( rv32_hazard hazard ( /* control in */ - .decode_rs1_in(decode_rs1), - .decode_rs2_in(decode_rs2), + .decode_rs1_in(decode_rs1_unreg), + .decode_rs2_in(decode_rs2_unreg), + + .decode_mem_read_en_in(decode_mem_read_en), + .decode_rd_in(decode_rd), + .decode_rd_writeback_in(decode_rd_writeback), .execute_mem_read_en_in(execute_mem_read_en), .execute_rd_in(execute_rd), .execute_rd_writeback_in(execute_rd_writeback), .mem_branch_taken_in(mem_branch_taken), - .mem_read_en_in(mem_read_en), - .mem_rd_in(mem_rd), - .mem_rd_writeback_in(mem_rd_writeback), /* control out */ .fetch_stall_out(fetch_stall), @@ -100,6 +101,10 @@ module rv32 ( /* data in (from writeback) */ .rd_value_in(mem_rd_value), + /* control out (to hazard) */ + .rs1_unreg_out(decode_rs1_unreg), + .rs2_unreg_out(decode_rs2_unreg), + /* control out */ .rs1_out(decode_rs1), .rs2_out(decode_rs2), @@ -123,6 +128,10 @@ module rv32 ( .imm_out(decode_imm) ); + /* decode -> hazard control */ + logic [4:0] decode_rs1_unreg; + logic [4:0] decode_rs2_unreg; + /* decode -> execute control */ logic [4:0] decode_rs1; logic [4:0] decode_rs2; diff --git a/rv32_decode.sv b/rv32_decode.sv index ebf4f87..9b47242 100644 --- a/rv32_decode.sv +++ b/rv32_decode.sv @@ -25,6 +25,10 @@ module rv32_decode ( /* data in (from writeback) */ input [31:0] rd_value_in, + /* control out (to hazard) */ + output [4:0] rs1_unreg_out, + output [4:0] rs2_unreg_out, + /* control out */ output valid_out, output [4:0] rs1_out, @@ -65,6 +69,9 @@ module rv32_decode ( logic [31:0] shamt = {27'bx, rs2}; + assign rs1_unreg_out = rs1; + assign rs2_unreg_out = rs2; + rv32_regs regs ( .clk(clk), .stall_in(stall_in), diff --git a/rv32_hazard.sv b/rv32_hazard.sv index 6ff4f8f..81508e6 100644 --- a/rv32_hazard.sv +++ b/rv32_hazard.sv @@ -6,14 +6,15 @@ module rv32_hazard ( input [4:0] decode_rs1_in, input [4:0] decode_rs2_in, + input decode_mem_read_en_in, + input [4:0] decode_rd_in, + input decode_rd_writeback_in, + input execute_mem_read_en_in, input [4:0] execute_rd_in, input execute_rd_writeback_in, input mem_branch_taken_in, - input mem_read_en_in, - input [4:0] mem_rd_in, - input mem_rd_writeback_in, /* control out */ output fetch_stall_out, @@ -28,21 +29,21 @@ module rv32_hazard ( output mem_stall_out, output mem_flush_out ); - logic decode_wait_for_mem_read; + logic fetch_wait_for_mem_read; always_comb begin - if ((decode_rs1_in == execute_rd_in || decode_rs2_in == execute_rd_in) && |execute_rd_in && execute_mem_read_en_in && execute_rd_writeback_in) - decode_wait_for_mem_read = 1; - else if ((decode_rs1_in == mem_rd_in || decode_rs2_in == mem_rd_in) && |mem_rd_in && mem_read_en_in && mem_rd_writeback_in) - decode_wait_for_mem_read = 1; + if ((decode_rs1_in == decode_rd_in || decode_rs2_in == decode_rd_in) && |decode_rd_in && decode_mem_read_en_in && decode_rd_writeback_in) + fetch_wait_for_mem_read = 1; + else if ((decode_rs1_in == execute_rd_in || decode_rs2_in == execute_rd_in) && |execute_rd_in && execute_mem_read_en_in && execute_rd_writeback_in) + fetch_wait_for_mem_read = 1; else - decode_wait_for_mem_read = 0; + fetch_wait_for_mem_read = 0; end - assign fetch_stall_out = decode_stall_out; + assign fetch_stall_out = decode_stall_out || fetch_wait_for_mem_read; assign fetch_flush_out = 0; - assign decode_stall_out = execute_stall_out || decode_wait_for_mem_read; + assign decode_stall_out = execute_stall_out; assign decode_flush_out = fetch_stall_out || mem_branch_taken_in; assign execute_stall_out = mem_stall_out;