From 29e4c40af4b5fa60148e38b23cc5a0b24036bef4 Mon Sep 17 00:00:00 2001
From: Graham Edgecombe <gpe@grahamedgecombe.com>
Date: Sun, 3 Dec 2017 19:27:41 +0000
Subject: [PATCH] Remove clock input from ALU and branch PC mux

---
 rv32_alu.sv     | 26 ++++++++++++--------------
 rv32_branch.sv  |  5 +----
 rv32_execute.sv | 14 ++++++++------
 3 files changed, 21 insertions(+), 24 deletions(-)

diff --git a/rv32_alu.sv b/rv32_alu.sv
index 07c019e..19179d3 100644
--- a/rv32_alu.sv
+++ b/rv32_alu.sv
@@ -4,8 +4,6 @@
 `include "rv32_alu_ops.sv"
 
 module rv32_alu (
-    input clk,
-
     /* control in */
     input [3:0] op_in,
     input sub_sra_in,
@@ -39,19 +37,19 @@ module rv32_alu (
     logic lt  = sign != ovf;
     logic ltu = carry;
 
-    always_ff @(posedge clk) begin
+    always_comb begin
         case (op_in)
-            RV32_ALU_OP_ADD_SUB: result_out <= add_sub[31:0];
-            RV32_ALU_OP_XOR:     result_out <= src1 ^ src2;
-            RV32_ALU_OP_OR:      result_out <= src1 | src2;
-            RV32_ALU_OP_AND:     result_out <= src1 & src2;
-            RV32_ALU_OP_SLL:     result_out <= src1 << shamt;
-            RV32_ALU_OP_SRL_SRA: result_out <= srl_sra;
-            RV32_ALU_OP_SLT:     result_out <= {31'b0, lt};
-            RV32_ALU_OP_SLTU:    result_out <= {31'b0, ltu};
-            RV32_ALU_OP_SRC1P4:  result_out <= src1 + 4;
-            RV32_ALU_OP_SRC2:    result_out <= src2;
-            default:             result_out <= 32'bx;
+            RV32_ALU_OP_ADD_SUB: result_out = add_sub[31:0];
+            RV32_ALU_OP_XOR:     result_out = src1 ^ src2;
+            RV32_ALU_OP_OR:      result_out = src1 | src2;
+            RV32_ALU_OP_AND:     result_out = src1 & src2;
+            RV32_ALU_OP_SLL:     result_out = src1 << shamt;
+            RV32_ALU_OP_SRL_SRA: result_out = srl_sra;
+            RV32_ALU_OP_SLT:     result_out = {31'b0, lt};
+            RV32_ALU_OP_SLTU:    result_out = {31'b0, ltu};
+            RV32_ALU_OP_SRC1P4:  result_out = src1 + 4;
+            RV32_ALU_OP_SRC2:    result_out = src2;
+            default:             result_out = 32'bx;
         endcase
     end
 endmodule
diff --git a/rv32_branch.sv b/rv32_branch.sv
index 0fb8b8c..a88a80e 100644
--- a/rv32_branch.sv
+++ b/rv32_branch.sv
@@ -4,8 +4,6 @@
 `include "rv32_branch_ops.sv"
 
 module rv32_branch_pc_mux (
-    input clk,
-
     /* control in */
     input pc_src_in,
 
@@ -19,8 +17,7 @@ module rv32_branch_pc_mux (
 );
     logic [31:0] pc = (pc_src_in ? rs1_value_in : pc_in) + imm_in;
 
-    always_ff @(posedge clk)
-        pc_out <= {pc[31:1], 1'b0};
+    assign pc_out = {pc[31:1], 1'b0};
 endmodule
 
 module rv32_branch (
diff --git a/rv32_execute.sv b/rv32_execute.sv
index 15c4db3..dc27889 100644
--- a/rv32_execute.sv
+++ b/rv32_execute.sv
@@ -69,9 +69,9 @@ module rv32_execute (
             rs2_value = rs2_value_in;
     end
 
-    rv32_alu alu (
-        .clk(clk),
+    logic [31:0] result;
 
+    rv32_alu alu (
         /* control in */
         .op_in(alu_op_in),
         .sub_sra_in(alu_sub_sra_in),
@@ -85,12 +85,12 @@ module rv32_execute (
         .imm_in(imm_in),
 
         /* data out */
-        .result_out(result_out)
+        .result_out(result)
     );
 
-    rv32_branch_pc_mux branch_pc_mux (
-        .clk(clk),
+    logic [31:0] branch_pc;
 
+    rv32_branch_pc_mux branch_pc_mux (
         /* control in */
         .pc_src_in(branch_pc_src_in),
 
@@ -100,7 +100,7 @@ module rv32_execute (
         .imm_in(imm_in),
 
         /* data out */
-        .pc_out(branch_pc_out)
+        .pc_out(branch_pc)
     );
 
     always_ff @(posedge clk) begin
@@ -111,7 +111,9 @@ module rv32_execute (
         branch_op_out <= branch_op_in;
         rd_out <= rd_in;
         rd_writeback_out <= rd_writeback_in;
+        result_out <= result;
         rs2_value_out <= rs2_value_in;
+        branch_pc_out <= branch_pc;
     end
 endmodule