From 3539f67764985ade980acabfe3ea69f80a16e43a Mon Sep 17 00:00:00 2001
From: Graham Edgecombe <gpe@grahamedgecombe.com>
Date: Sun, 3 Dec 2017 19:23:42 +0000
Subject: [PATCH] Replace wire with logic

---
 clk_div.sv     | 2 +-
 rv32_branch.sv | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/clk_div.sv b/clk_div.sv
index 16860f9..dce7908 100644
--- a/clk_div.sv
+++ b/clk_div.sv
@@ -7,7 +7,7 @@ module clk_div #(
     input clk_in,
     output clk_out
 );
-    wire [LOG_DIVISOR-1:0] q;
+    logic [LOG_DIVISOR-1:0] q;
 
     always_ff @(posedge clk_in)
         q <= q + 1;
diff --git a/rv32_branch.sv b/rv32_branch.sv
index 728f3e7..0fb8b8c 100644
--- a/rv32_branch.sv
+++ b/rv32_branch.sv
@@ -33,7 +33,7 @@ module rv32_branch (
     /* control out */
     output taken_out
 );
-    wire non_zero = |result_in;
+    logic non_zero = |result_in;
 
     always_comb begin
         case (op_in)