diff --git a/rv32.sv b/rv32.sv index acbf5c3..5c1d5ce 100644 --- a/rv32.sv +++ b/rv32.sv @@ -25,7 +25,7 @@ module rv32 ( .decode_rs1_in(decode_rs1_unreg), .decode_rs2_in(decode_rs2_unreg), - .decode_mem_read_en_in(decode_mem_read_en), + .decode_mem_read_in(decode_mem_read), .decode_rd_in(decode_rd), .decode_rd_writeback_in(decode_rd_writeback), @@ -112,8 +112,8 @@ module rv32 ( .alu_sub_sra_out(decode_alu_sub_sra), .alu_src1_out(decode_alu_src1), .alu_src2_out(decode_alu_src2), - .mem_read_en_out(decode_mem_read_en), - .mem_write_en_out(decode_mem_write_en), + .mem_read_out(decode_mem_read), + .mem_write_out(decode_mem_write), .mem_width_out(decode_mem_width), .mem_zero_extend_out(decode_mem_zero_extend), .branch_op_out(decode_branch_op), @@ -139,8 +139,8 @@ module rv32 ( logic decode_alu_sub_sra; logic decode_alu_src1; logic decode_alu_src2; - logic decode_mem_read_en; - logic decode_mem_write_en; + logic decode_mem_read; + logic decode_mem_write; logic [1:0] decode_mem_width; logic decode_mem_zero_extend; logic [1:0] decode_branch_op; @@ -168,8 +168,8 @@ module rv32 ( .alu_sub_sra_in(decode_alu_sub_sra), .alu_src1_in(decode_alu_src1), .alu_src2_in(decode_alu_src2), - .mem_read_en_in(decode_mem_read_en), - .mem_write_en_in(decode_mem_write_en), + .mem_read_in(decode_mem_read), + .mem_write_in(decode_mem_write), .mem_width_in(decode_mem_width), .mem_zero_extend_in(decode_mem_zero_extend), .branch_op_in(decode_branch_op), @@ -191,8 +191,8 @@ module rv32 ( .writeback_rd_value_in(mem_rd_value), /* control out */ - .mem_read_en_out(execute_mem_read_en), - .mem_write_en_out(execute_mem_write_en), + .mem_read_out(execute_mem_read), + .mem_write_out(execute_mem_write), .mem_width_out(execute_mem_width), .mem_zero_extend_out(execute_mem_zero_extend), .branch_op_out(execute_branch_op), @@ -206,8 +206,8 @@ module rv32 ( ); /* execute -> mem control */ - logic execute_mem_read_en; - logic execute_mem_write_en; + logic execute_mem_read; + logic execute_mem_write; logic [1:0] execute_mem_width; logic execute_mem_zero_extend; logic [1:0] execute_branch_op; @@ -227,8 +227,8 @@ module rv32 ( .flush_in(mem_flush), /* control in */ - .read_en_in(execute_mem_read_en), - .write_en_in(execute_mem_write_en), + .read_in(execute_mem_read), + .write_in(execute_mem_write), .width_in(execute_mem_width), .zero_extend_in(execute_mem_zero_extend), .branch_op_in(execute_branch_op), diff --git a/rv32_decode.sv b/rv32_decode.sv index 1fc8038..3780a8c 100644 --- a/rv32_decode.sv +++ b/rv32_decode.sv @@ -37,8 +37,8 @@ module rv32_decode ( output alu_sub_sra_out, output alu_src1_out, output alu_src2_out, - output mem_read_en_out, - output mem_write_en_out, + output mem_read_out, + output mem_write_out, output [1:0] mem_width_out, output mem_zero_extend_out, output [1:0] branch_op_out, @@ -99,8 +99,8 @@ module rv32_decode ( alu_sub_sra_out <= 1'bx; alu_src1_out <= 1'bx; alu_src2_out <= 1'bx; - mem_read_en_out <= 0; - mem_write_en_out <= 0; + mem_read_out <= 0; + mem_write_out <= 0; mem_width_out <= 2'bx; mem_zero_extend_out <= 1'bx; branch_op_out <= RV32_BRANCH_OP_NEVER; @@ -223,7 +223,7 @@ module rv32_decode ( alu_sub_sra_out <= 0; alu_src1_out <= RV32_ALU_SRC1_REG; alu_src2_out <= RV32_ALU_SRC2_IMM; - mem_read_en_out <= 1; + mem_read_out <= 1; mem_width_out <= RV32_MEM_WIDTH_BYTE; mem_zero_extend_out <= 0; rd_writeback_out <= 1; @@ -236,7 +236,7 @@ module rv32_decode ( alu_sub_sra_out <= 0; alu_src1_out <= RV32_ALU_SRC1_REG; alu_src2_out <= RV32_ALU_SRC2_IMM; - mem_read_en_out <= 1; + mem_read_out <= 1; mem_width_out <= RV32_MEM_WIDTH_HALF; mem_zero_extend_out <= 0; rd_writeback_out <= 1; @@ -249,7 +249,7 @@ module rv32_decode ( alu_sub_sra_out <= 0; alu_src1_out <= RV32_ALU_SRC1_REG; alu_src2_out <= RV32_ALU_SRC2_IMM; - mem_read_en_out <= 1; + mem_read_out <= 1; mem_width_out <= RV32_MEM_WIDTH_WORD; rd_writeback_out <= 1; imm_out <= imm_i; @@ -261,7 +261,7 @@ module rv32_decode ( alu_sub_sra_out <= 0; alu_src1_out <= RV32_ALU_SRC1_REG; alu_src2_out <= RV32_ALU_SRC2_IMM; - mem_read_en_out <= 1; + mem_read_out <= 1; mem_width_out <= RV32_MEM_WIDTH_BYTE; mem_zero_extend_out <= 1; rd_writeback_out <= 1; @@ -274,7 +274,7 @@ module rv32_decode ( alu_sub_sra_out <= 0; alu_src1_out <= RV32_ALU_SRC1_REG; alu_src2_out <= RV32_ALU_SRC2_IMM; - mem_read_en_out <= 1; + mem_read_out <= 1; mem_width_out <= RV32_MEM_WIDTH_HALF; mem_zero_extend_out <= 1; rd_writeback_out <= 1; @@ -287,7 +287,7 @@ module rv32_decode ( alu_sub_sra_out <= 0; alu_src1_out <= RV32_ALU_SRC1_REG; alu_src2_out <= RV32_ALU_SRC2_IMM; - mem_write_en_out <= 1; + mem_write_out <= 1; mem_width_out <= RV32_MEM_WIDTH_BYTE; imm_out <= imm_s; end @@ -298,7 +298,7 @@ module rv32_decode ( alu_sub_sra_out <= 0; alu_src1_out <= RV32_ALU_SRC1_REG; alu_src2_out <= RV32_ALU_SRC2_IMM; - mem_write_en_out <= 1; + mem_write_out <= 1; mem_width_out <= RV32_MEM_WIDTH_HALF; imm_out <= imm_s; end @@ -309,7 +309,7 @@ module rv32_decode ( alu_sub_sra_out <= 0; alu_src1_out <= RV32_ALU_SRC1_REG; alu_src2_out <= RV32_ALU_SRC2_IMM; - mem_write_en_out <= 1; + mem_write_out <= 1; mem_width_out <= RV32_MEM_WIDTH_WORD; imm_out <= imm_s; end @@ -496,8 +496,8 @@ module rv32_decode ( endcase if (flush_in) begin - mem_read_en_out <= 0; - mem_write_en_out <= 0; + mem_read_out <= 0; + mem_write_out <= 0; branch_op_out <= RV32_BRANCH_OP_NEVER; rd_writeback_out <= 0; end diff --git a/rv32_execute.sv b/rv32_execute.sv index 03019c9..c088eff 100644 --- a/rv32_execute.sv +++ b/rv32_execute.sv @@ -18,8 +18,8 @@ module rv32_execute ( input alu_sub_sra_in, input alu_src1_in, input alu_src2_in, - input mem_read_en_in, - input mem_write_en_in, + input mem_read_in, + input mem_write_in, input [1:0] mem_width_in, input mem_zero_extend_in, input [1:0] branch_op_in, @@ -41,8 +41,8 @@ module rv32_execute ( input [31:0] writeback_rd_value_in, /* control out */ - output mem_read_en_out, - output mem_write_en_out, + output mem_read_out, + output mem_write_out, output [1:0] mem_width_out, output mem_zero_extend_out, output [1:0] branch_op_out, @@ -109,8 +109,8 @@ module rv32_execute ( always_ff @(posedge clk) begin if (!stall_in) begin - mem_read_en_out <= mem_read_en_in; - mem_write_en_out <= mem_write_en_in; + mem_read_out <= mem_read_in; + mem_write_out <= mem_write_in; mem_width_out <= mem_width_in; mem_zero_extend_out <= mem_zero_extend_in; branch_op_out <= branch_op_in; @@ -121,8 +121,8 @@ module rv32_execute ( branch_pc_out <= branch_pc; if (flush_in) begin - mem_read_en_out <= 0; - mem_write_en_out <= 0; + mem_read_out <= 0; + mem_write_out <= 0; branch_op_out <= RV32_BRANCH_OP_NEVER; rd_writeback_out <= 0; end diff --git a/rv32_hazard.sv b/rv32_hazard.sv index 7733029..b67f68e 100644 --- a/rv32_hazard.sv +++ b/rv32_hazard.sv @@ -6,7 +6,7 @@ module rv32_hazard ( input [4:0] decode_rs1_in, input [4:0] decode_rs2_in, - input decode_mem_read_en_in, + input decode_mem_read_in, input [4:0] decode_rd_in, input decode_rd_writeback_in, @@ -25,7 +25,7 @@ module rv32_hazard ( output mem_stall_out, output mem_flush_out ); - logic fetch_wait_for_mem_read = (decode_rs1_in == decode_rd_in || decode_rs2_in == decode_rd_in) && |decode_rd_in && decode_mem_read_en_in && decode_rd_writeback_in; + logic fetch_wait_for_mem_read = (decode_rs1_in == decode_rd_in || decode_rs2_in == decode_rd_in) && |decode_rd_in && decode_mem_read_in && decode_rd_writeback_in; assign fetch_stall_out = decode_stall_out || fetch_wait_for_mem_read; assign fetch_flush_out = 0; diff --git a/rv32_mem.sv b/rv32_mem.sv index a8618d1..55e21a4 100644 --- a/rv32_mem.sv +++ b/rv32_mem.sv @@ -15,8 +15,8 @@ module rv32_mem ( input flush_in, /* control in */ - input read_en_in, - input write_en_in, + input read_in, + input write_in, input [1:0] width_in, input zero_extend_in, input [1:0] branch_op_in, @@ -63,7 +63,7 @@ module rv32_mem ( assign address_out = result_in; always_comb begin - if (write_en_in) begin + if (write_in) begin case (width_in) RV32_MEM_WIDTH_WORD: begin write_value_out = rs2_value_in; @@ -117,7 +117,7 @@ module rv32_mem ( rd_out <= rd_in; rd_writeback_out <= rd_writeback_in; - if (read_en_in) begin + if (read_in) begin case (width_in) RV32_MEM_WIDTH_WORD: begin rd_value_out <= read_value_in;