From 4d9d405c059d3f469a57ba8d21a9e3c42fdba4e3 Mon Sep 17 00:00:00 2001
From: Graham Edgecombe <gpe@grahamedgecombe.com>
Date: Thu, 7 Dec 2017 20:22:11 +0000
Subject: [PATCH] Fix TX ready output

---
 uart.sv | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/uart.sv b/uart.sv
index a89b6bd..21c3d36 100644
--- a/uart.sv
+++ b/uart.sv
@@ -43,7 +43,7 @@ module uart (
                     read_value_out = {16'b0, clk_div};
                 end
                 UART_REG_STATUS: begin
-                    read_value_out = {31'b0, |tx_bits};
+                    read_value_out = {31'b0, ~|tx_bits};
                 end
                 UART_REG_DATA: begin
                     read_value_out = 0;