diff --git a/rv32_alu.sv b/rv32_alu.sv
index 15faaff..beefbcb 100644
--- a/rv32_alu.sv
+++ b/rv32_alu.sv
@@ -46,6 +46,7 @@ module rv32_alu (
             RV32_ALU_OP_SRL_SRA: result_out <= srl_sra;
             RV32_ALU_OP_SLT:     result_out <= {31'b0, lt};
             RV32_ALU_OP_SLTU:    result_out <= {31'b0, ltu};
+            RV32_ALU_OP_SRC1P4:  result_out <= src1 + 4;
             RV32_ALU_OP_SRC2:    result_out <= src2;
             default:             result_out <= 32'bx;
         endcase
diff --git a/rv32_alu_ops.sv b/rv32_alu_ops.sv
index 46ee50a..2afb676 100644
--- a/rv32_alu_ops.sv
+++ b/rv32_alu_ops.sv
@@ -6,7 +6,8 @@ localparam RV32_ALU_OP_SLL     = 4'b0100;
 localparam RV32_ALU_OP_SRL_SRA = 4'b0101;
 localparam RV32_ALU_OP_SLT     = 4'b0110;
 localparam RV32_ALU_OP_SLTU    = 4'b0111;
-localparam RV32_ALU_OP_SRC2    = 4'b1000;
+localparam RV32_ALU_OP_SRC1P4  = 4'b1000;
+localparam RV32_ALU_OP_SRC2    = 4'b1001;
 
 localparam RV32_ALU_SRC1_REG = 1'b0;
 localparam RV32_ALU_SRC1_PC  = 1'b1;
diff --git a/rv32_decode.sv b/rv32_decode.sv
index d570589..be68be0 100644
--- a/rv32_decode.sv
+++ b/rv32_decode.sv
@@ -81,11 +81,15 @@ module rv32_decode (
             {RV32_OPCODE_JAL, RV32_FUNCT3_ANY, RV32_FUNCT7_ANY}: begin
                 /* JAL */
                 valid_out <= 1;
+                alu_op_out <= RV32_ALU_OP_SRC1P4;
+                alu_src1_out <= RV32_ALU_SRC1_PC;
                 imm_out <= imm_j;
             end
             {RV32_OPCODE_JALR, RV32_FUNCT3_ZERO, RV32_FUNCT7_ANY}: begin
                 /* JALR */
                 valid_out <= 1;
+                alu_op_out <= RV32_ALU_OP_SRC1P4;
+                alu_src1_out <= RV32_ALU_SRC1_PC;
                 imm_out <= imm_i;
             end
             {RV32_OPCODE_BRANCH, RV32_FUNCT3_BRANCH_BEQ, RV32_FUNCT7_ANY}: begin