From 66089359fea9c66cb61b22307a044f4e40b7637d Mon Sep 17 00:00:00 2001
From: Graham Edgecombe <gpe@grahamedgecombe.com>
Date: Thu, 7 Dec 2017 21:32:25 +0000
Subject: [PATCH] Make the meaning of the TX write ready status bit clearer

---
 uart.sv | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/uart.sv b/uart.sv
index 54fcece..cbe1539 100644
--- a/uart.sv
+++ b/uart.sv
@@ -38,6 +38,8 @@ module uart (
     logic [3:0] tx_bits;
     logic [9:0] tx_buf;
 
+    logic tx_write_ready = ~|tx_bits;
+
     initial
         tx_buf[0] = 1;
 
@@ -50,7 +52,7 @@ module uart (
                     read_value_out = {16'b0, clk_div};
                 end
                 UART_REG_STATUS: begin
-                    read_value_out = {30'b0, rx_read_ready, ~|tx_bits};
+                    read_value_out = {30'b0, rx_read_ready, tx_write_ready};
                 end
                 UART_REG_DATA: begin
                     read_value_out = {{24{~rx_read_ready}}, rx_read_ready ? rx_read_buf : 8'b0};