From 70d72331a7cff9f15e6d05506dd93f64c8b59311 Mon Sep 17 00:00:00 2001
From: Graham Edgecombe <gpe@grahamedgecombe.com>
Date: Sun, 3 Dec 2017 21:51:07 +0000
Subject: [PATCH] Order outputs consistently in the decode stage

---
 rv32_decode.sv | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/rv32_decode.sv b/rv32_decode.sv
index 8bffbee..db48817 100644
--- a/rv32_decode.sv
+++ b/rv32_decode.sv
@@ -83,23 +83,23 @@ module rv32_decode (
 
     always_ff @(posedge clk) begin
         if (!stall) begin
+            valid_out <= 0;
             rs1_out <= rs1;
             rs2_out <= rs2;
-            rd_out <= rd;
-            pc_out <= pc_in;
-
-            valid_out <= 0;
             alu_op_out <= 4'bx;
             alu_sub_sra_out <= 1'bx;
             alu_src1_out <= 1'bx;
             alu_src2_out <= 1'bx;
-            rd_writeback_out <= 0;
             mem_read_en_out <= 0;
             mem_write_en_out <= 0;
             mem_width_out <= 2'bx;
             mem_zero_extend_out <= 1'bx;
             branch_op_out <= RV32_BRANCH_OP_NEVER;
             branch_pc_src_out <= 1'bx;
+            rd_out <= rd;
+            rd_writeback_out <= 0;
+
+            pc_out <= pc_in;
             imm_out <= 32'bx;
 
             casez ({opcode, funct3, funct7})