From 82394bce1cf3819fabe28d0c4307e5b238f81254 Mon Sep 17 00:00:00 2001 From: Graham Edgecombe Date: Wed, 6 Dec 2017 15:36:46 +0000 Subject: [PATCH] Add read_out signal to the memory bus This is required to implement reads with side effects (e.g. reading from the UART receive buffer). --- rv32.sv | 2 ++ rv32_mem.sv | 2 ++ top.sv | 2 ++ 3 files changed, 6 insertions(+) diff --git a/rv32.sv b/rv32.sv index cefab82..e926c3d 100644 --- a/rv32.sv +++ b/rv32.sv @@ -11,6 +11,7 @@ module rv32 ( input clk, /* control out (memory bus) */ + output read_out, output [3:0] write_mask_out, /* data in (memory bus) */ @@ -249,6 +250,7 @@ module rv32 ( .rd_write_out(mem_rd_write), /* control out (to memory bus) */ + .read_out(read_out), .write_mask_out(write_mask_out), /* data out */ diff --git a/rv32_mem.sv b/rv32_mem.sv index 5c6f14e..564280c 100644 --- a/rv32_mem.sv +++ b/rv32_mem.sv @@ -37,6 +37,7 @@ module rv32_mem ( output rd_write_out, /* control out (to memory bus) */ + output read_out, output [3:0] write_mask_out, /* data out */ @@ -60,6 +61,7 @@ module rv32_mem ( assign branch_pc_out = branch_pc_in; + assign read_out = read_in; assign address_out = result_in; always_comb begin diff --git a/top.sv b/top.sv index 6dcd137..a6abb97 100644 --- a/top.sv +++ b/top.sv @@ -60,6 +60,7 @@ module top ( .clk(pll_clk), /* control out */ + .read_out(mem_read), .write_mask_out(mem_write_mask), /* data in */ @@ -71,6 +72,7 @@ module top ( ); /* memory bus control */ + logic mem_read; logic [3:0] mem_write_mask; /* memory bus data */