From 98811cce8667ddf509a127a67045a8b0694ae423 Mon Sep 17 00:00:00 2001
From: Graham Edgecombe <gpe@grahamedgecombe.com>
Date: Sun, 31 Dec 2017 15:38:07 +0000
Subject: [PATCH] Explicitly instantiate all registers to 0

---
 rv32_regs.sv | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/rv32_regs.sv b/rv32_regs.sv
index df3eccc..4d8ee23 100644
--- a/rv32_regs.sv
+++ b/rv32_regs.sv
@@ -20,6 +20,14 @@ module rv32_regs (
 );
     logic [31:0] regs [31:0];
 
+    generate
+        genvar i;
+        for (i = 0; i < 32; i = i+1) begin
+            initial
+                regs[i] <= 0;
+        end
+    endgenerate
+
     always_ff @(posedge clk) begin
         if (!stall_in) begin
             rs1_value_out <= regs[rs1_in];