From 9c8dfd1b826907dde5483b0aee4701294edf590e Mon Sep 17 00:00:00 2001
From: Graham Edgecombe <gpe@grahamedgecombe.com>
Date: Sun, 10 Dec 2017 09:25:18 +0000
Subject: [PATCH] Replace top.sv with $(TOP).sv

---
 Makefile | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Makefile b/Makefile
index 5150915..24da96e 100644
--- a/Makefile
+++ b/Makefile
@@ -42,7 +42,7 @@ $(BLIF): $(YS) $(SRC) progmem_syn.hex
 	yosys $(QUIET) -s $<
 
 check: $(SRC)
-	iverilog -Wall -t null -g2012 `yosys-config --datdir/ice40/cells_sim.v` top.sv
+	iverilog -Wall -t null -g2012 `yosys-config --datdir/ice40/cells_sim.v` $(TOP).sv
 
 $(ASC_SYN): $(BLIF) $(PCF)
 	arachne-pnr $(QUIET) -d $(DEVICE) -P $(PACKAGE) -o $@ -p $(PCF) $<