diff --git a/Makefile b/Makefile
index a1ec0cb..b5e6f98 100644
--- a/Makefile
+++ b/Makefile
@@ -3,7 +3,7 @@ PLL      = pll.sv
 SRC      = $(sort $(wildcard *.sv) $(PLL))
 TOP      = top
 SV       = $(TOP).sv
-YS       = $(TOP).ys
+TCL       := $(TOP).tcl
 YS_ICE40 = `yosys-config --datdir/ice40/cells_sim.v`
 BLIF     = $(TOP).blif
 ASC_SYN  = $(TOP)_syn.asc
@@ -30,6 +30,14 @@ OBJCOPY  = $(TARGET)-objcopy
 
 all: $(BIN)
 
+upduino:	SPEED=up
+upduino:	DEVICE=5k
+upduino:	PACKAGE=sg48
+upduino:	PCF=ice40up5k-upduino.pcf
+upduino:	FREQ_OSC=48
+upduino: clean all
+	@echo "executing yosys script $(YS)"
+
 clean:
 	$(RM) $(BLIF) $(ASC_SYN) $(ASC) $(BIN) $(PLL) $(TIME_RPT) $(STAT) progmem_syn.hex progmem.hex progmem.o start.o progmem
 
@@ -46,8 +54,9 @@ progmem_syn.hex:
 $(PLL):
 	icepll $(QUIET) -i $(FREQ_OSC) -o $(FREQ_PLL) -m -f $@
 
-$(BLIF): $(YS) $(SRC) progmem_syn.hex
-	yosys $(QUIET) -s $<
+$(BLIF): $(TCL) $(SRC) progmem_syn.hex
+	@echo "device is $(DEVICE)"
+	IC=$(SPEED)$(DEVICE) yosys $(QUIET) $<
 
 syntax: $(SRC) progmem_syn.hex
 	iverilog -Wall -t null -g2012 $(YS_ICE40) $(SV)
diff --git a/top.sv b/top.sv
index c8f2c0b..8e9ccc8 100644
--- a/top.sv
+++ b/top.sv
@@ -6,7 +6,9 @@
 `include "uart.sv"
 
 module top (
+`ifndef up5k
     input clk,
+`endif
 
     /* serial flash */
     output logic flash_clk,
@@ -29,6 +31,15 @@ module top (
     logic flash_io1_in;
     logic flash_io1_out;
 
+`ifdef up5k
+    wire clk;
+    SB_HFOSC inthosc (
+        .CLKHFPU(1'b1),
+        .CLKHFEN(1'b1),
+        .CLKHF(clk)
+    );
+`endif
+
     SB_IO #(
         .PIN_TYPE(6'b1010_01)
     ) flash_io [1:0] (
diff --git a/top.ys b/top.ys
deleted file mode 100644
index 28173f7..0000000
--- a/top.ys
+++ /dev/null
@@ -1,6 +0,0 @@
-read_verilog -noautowire -sv top.sv
-proc
-opt -full
-alumacc
-share -aggressive
-synth_ice40 -abc2 -top top -blif top.blif