From d6f5bb2218811269caf1cb3f26106aa4fcebc589 Mon Sep 17 00:00:00 2001
From: Graham Edgecombe <gpe@grahamedgecombe.com>
Date: Tue, 12 Dec 2017 21:53:59 +0000
Subject: [PATCH] Add initial support for SYSTEM instructions to the decoder

---
 rv32_decode.sv  | 35 +++++++++++++++++++++++++++++++++++
 rv32_opcodes.sv | 11 +++++++++++
 2 files changed, 46 insertions(+)

diff --git a/rv32_decode.sv b/rv32_decode.sv
index badd213..27b6364 100644
--- a/rv32_decode.sv
+++ b/rv32_decode.sv
@@ -68,6 +68,7 @@ module rv32_decode (
     logic [31:0] imm_j;
 
     logic [31:0] shamt;
+    logic [31:0] zimm;
 
     assign funct7 = instr_in[31:25];
     assign rs2    = instr_in[24:20];
@@ -85,6 +86,7 @@ module rv32_decode (
     assign imm_j = {{12{sign}}, instr_in[19:12], instr_in[20],    instr_in[30:25], instr_in[24:21], 1'b0};
 
     assign shamt = {27'bx, rs2};
+    assign zimm  = {27'b0, rs1};
 
     assign rs1_unreg_out = rs1;
     assign rs2_unreg_out = rs2;
@@ -510,6 +512,39 @@ module rv32_decode (
                     /* FENCE.I */
                     valid_out <= 1;
                 end
+                {`RV32_OPCODE_SYSTEM, `RV32_FUNCT3_SYSTEM_PRIV, `RV32_FUNCT7_ANY}: begin
+                    // TODO: EBREAK/ECALL
+                end
+                {`RV32_OPCODE_SYSTEM, `RV32_FUNCT3_SYSTEM_CSRRW, `RV32_FUNCT7_ANY}: begin
+                    /* CSRRW */
+                    valid_out <= 1;
+                    // TODO
+                end
+                {`RV32_OPCODE_SYSTEM, `RV32_FUNCT3_SYSTEM_CSRRS, `RV32_FUNCT7_ANY}: begin
+                    /* CSRRS */
+                    valid_out <= 1;
+                    // TODO
+                end
+                {`RV32_OPCODE_SYSTEM, `RV32_FUNCT3_SYSTEM_CSRRC, `RV32_FUNCT7_ANY}: begin
+                    /* CSRRC */
+                    valid_out <= 1;
+                    // TODO
+                end
+                {`RV32_OPCODE_SYSTEM, `RV32_FUNCT3_SYSTEM_CSRRWI, `RV32_FUNCT7_ANY}: begin
+                    /* CSRRWI */
+                    valid_out <= 1;
+                    // TODO
+                end
+                {`RV32_OPCODE_SYSTEM, `RV32_FUNCT3_SYSTEM_CSRRSI, `RV32_FUNCT7_ANY}: begin
+                    /* CSRRSI */
+                    valid_out <= 1;
+                    // TODO
+                end
+                {`RV32_OPCODE_SYSTEM, `RV32_FUNCT3_SYSTEM_CSRRCI, `RV32_FUNCT7_ANY}: begin
+                    /* CSRRCI */
+                    valid_out <= 1;
+                    // TODO
+                end
             endcase
 
             if (flush_in) begin
diff --git a/rv32_opcodes.sv b/rv32_opcodes.sv
index ec83b24..b67fdb3 100644
--- a/rv32_opcodes.sv
+++ b/rv32_opcodes.sv
@@ -45,12 +45,23 @@
 `define RV32_FUNCT3_MISC_MEM_FENCE   3'b000
 `define RV32_FUNCT3_MISC_MEM_FENCE_I 3'b001
 
+`define RV32_FUNCT3_SYSTEM_PRIV   3'b000
+`define RV32_FUNCT3_SYSTEM_CSRRW  3'b001
+`define RV32_FUNCT3_SYSTEM_CSRRS  3'b010
+`define RV32_FUNCT3_SYSTEM_CSRRC  3'b011
+`define RV32_FUNCT3_SYSTEM_CSRRWI 3'b101
+`define RV32_FUNCT3_SYSTEM_CSRRSI 3'b110
+`define RV32_FUNCT3_SYSTEM_CSRRCI 3'b111
+
 `define RV32_FUNCT7_ANY  7'b???????
 `define RV32_FUNCT7_ZERO 7'b0000000
 
 `define RV32_FUNCT7_OP_SRA 7'b0100000
 `define RV32_FUNCT7_OP_SUB 7'b0100000
 
+`define RV32_FUNCT12_SYSTEM_PRIV_ECALL  12'b000000000000
+`define RV32_FUNCT12_SYSTEM_PRIV_EBREAK 12'b000000000001
+
 `define RV32_INSTR_NOP {12'bx, 5'b0, 3'bx, 5'b0, `RV32_OPCODE_OP_IMM}
 
 `endif