diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml
index 09623d4..f24f25f 100644
--- a/.gitlab-ci.yml
+++ b/.gitlab-ci.yml
@@ -6,4 +6,4 @@ stages:
 build:
   stage: build
   script:
-    - make syntax time stat
+    - make YS_ICE40=/usr/share/yosys/ice40/cells_sim.v syntax time stat
diff --git a/Makefile b/Makefile
index 55c291b..a9fd34c 100644
--- a/Makefile
+++ b/Makefile
@@ -4,6 +4,7 @@ SRC      = $(sort $(wildcard *.sv) $(PLL))
 TOP      = top
 SV       = $(TOP).sv
 YS       = $(TOP).ys
+YS_ICE40 = `yosys-config --datdir/ice40/cells_sim.v`
 BLIF     = $(TOP).blif
 ASC_SYN  = $(TOP)_syn.asc
 ASC      = $(TOP).asc
@@ -43,7 +44,7 @@ $(BLIF): $(YS) $(SRC) progmem_syn.hex
 	yosys $(QUIET) -s $<
 
 syntax: $(SRC) progmem_syn.hex
-	iverilog -Wall -t null -g2012 `yosys-config --datdir/ice40/cells_sim.v` $(SV)
+	iverilog -Wall -t null -g2012 $(YS_ICE40) $(SV)
 
 $(ASC_SYN): $(BLIF) $(PCF)
 	arachne-pnr $(QUIET) -d $(DEVICE) -P $(PACKAGE) -o $@ -p $(PCF) $<