From e2a533babbea064d68cc3b89589a1a7d1f9df612 Mon Sep 17 00:00:00 2001 From: Graham Edgecombe Date: Sun, 3 Dec 2017 14:27:16 +0000 Subject: [PATCH] Access data memory on negative clock edge This will allow shifting, sign extension and zero extension logic to be placed after reads, so we can add support for the LB, LBU, LH and LHU opcodes. --- rv32_mem.sv | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/rv32_mem.sv b/rv32_mem.sv index c98e9dc..a9d7d38 100644 --- a/rv32_mem.sv +++ b/rv32_mem.sv @@ -44,16 +44,22 @@ module rv32_mem ( assign branch_pc_out = branch_pc_in; + logic [31:0] read_value; + + always_ff @(negedge clk) begin + read_value <= data_mem[result_in[31:2]]; + + if (write_en_in) + data_mem[result_in[31:2]] <= rs2_value_in; + end + always_ff @(posedge clk) begin read_en_out <= read_en_in; rd_out <= rd_in; rd_writeback_out <= rd_writeback_in; result_out <= result_in; - read_value_out <= data_mem[result_in[31:2]]; - - if (write_en_in) - data_mem[result_in[31:2]] <= rs2_value_in; + read_value_out <= read_value; end endmodule