diff --git a/rv32_alu.sv b/rv32_alu.sv index 807b717..757860e 100644 --- a/rv32_alu.sv +++ b/rv32_alu.sv @@ -1,22 +1,22 @@ `ifndef RV32_ALU `define RV32_ALU -localparam RV32_ALU_OP_ADD_SUB = 4'b0000; -localparam RV32_ALU_OP_XOR = 4'b0001; -localparam RV32_ALU_OP_OR = 4'b0010; -localparam RV32_ALU_OP_AND = 4'b0011; -localparam RV32_ALU_OP_SLL = 4'b0100; -localparam RV32_ALU_OP_SRL_SRA = 4'b0101; -localparam RV32_ALU_OP_SLT = 4'b0110; -localparam RV32_ALU_OP_SLTU = 4'b0111; -localparam RV32_ALU_OP_SRC1P4 = 4'b1000; -localparam RV32_ALU_OP_SRC2 = 4'b1001; +`define RV32_ALU_OP_ADD_SUB 4'b0000 +`define RV32_ALU_OP_XOR 4'b0001 +`define RV32_ALU_OP_OR 4'b0010 +`define RV32_ALU_OP_AND 4'b0011 +`define RV32_ALU_OP_SLL 4'b0100 +`define RV32_ALU_OP_SRL_SRA 4'b0101 +`define RV32_ALU_OP_SLT 4'b0110 +`define RV32_ALU_OP_SLTU 4'b0111 +`define RV32_ALU_OP_SRC1P4 4'b1000 +`define RV32_ALU_OP_SRC2 4'b1001 -localparam RV32_ALU_SRC1_REG = 1'b0; -localparam RV32_ALU_SRC1_PC = 1'b1; +`define RV32_ALU_SRC1_REG 1'b0 +`define RV32_ALU_SRC1_PC 1'b1 -localparam RV32_ALU_SRC2_REG = 1'b0; -localparam RV32_ALU_SRC2_IMM = 1'b1; +`define RV32_ALU_SRC2_REG 1'b0 +`define RV32_ALU_SRC2_IMM 1'b1 module rv32_alu ( /* control in */ @@ -54,17 +54,17 @@ module rv32_alu ( always_comb begin case (op_in) - RV32_ALU_OP_ADD_SUB: result_out = add_sub[31:0]; - RV32_ALU_OP_XOR: result_out = src1 ^ src2; - RV32_ALU_OP_OR: result_out = src1 | src2; - RV32_ALU_OP_AND: result_out = src1 & src2; - RV32_ALU_OP_SLL: result_out = src1 << shamt; - RV32_ALU_OP_SRL_SRA: result_out = srl_sra; - RV32_ALU_OP_SLT: result_out = {31'b0, lt}; - RV32_ALU_OP_SLTU: result_out = {31'b0, ltu}; - RV32_ALU_OP_SRC1P4: result_out = src1 + 4; - RV32_ALU_OP_SRC2: result_out = src2; - default: result_out = 32'bx; + `RV32_ALU_OP_ADD_SUB: result_out = add_sub[31:0]; + `RV32_ALU_OP_XOR: result_out = src1 ^ src2; + `RV32_ALU_OP_OR: result_out = src1 | src2; + `RV32_ALU_OP_AND: result_out = src1 & src2; + `RV32_ALU_OP_SLL: result_out = src1 << shamt; + `RV32_ALU_OP_SRL_SRA: result_out = srl_sra; + `RV32_ALU_OP_SLT: result_out = {31'b0, lt}; + `RV32_ALU_OP_SLTU: result_out = {31'b0, ltu}; + `RV32_ALU_OP_SRC1P4: result_out = src1 + 4; + `RV32_ALU_OP_SRC2: result_out = src2; + default: result_out = 32'bx; endcase end endmodule diff --git a/rv32_branch.sv b/rv32_branch.sv index 0129420..5f1eae5 100644 --- a/rv32_branch.sv +++ b/rv32_branch.sv @@ -1,13 +1,13 @@ `ifndef RV32_BRANCH `define RV32_BRANCH -localparam RV32_BRANCH_OP_NEVER = 3'b00; -localparam RV32_BRANCH_OP_ZERO = 3'b01; -localparam RV32_BRANCH_OP_NON_ZERO = 3'b10; -localparam RV32_BRANCH_OP_ALWAYS = 3'b11; +`define RV32_BRANCH_OP_NEVER 3'b00 +`define RV32_BRANCH_OP_ZERO 3'b01 +`define RV32_BRANCH_OP_NON_ZERO 3'b10 +`define RV32_BRANCH_OP_ALWAYS 3'b11 -localparam RV32_BRANCH_PC_SRC_IMM = 1'b0; -localparam RV32_BRANCH_PC_SRC_REG = 1'b1; +`define RV32_BRANCH_PC_SRC_IMM 1'b0 +`define RV32_BRANCH_PC_SRC_REG 1'b1 module rv32_branch_pc_mux ( /* control in */ @@ -40,10 +40,10 @@ module rv32_branch ( always_comb begin case (op_in) - RV32_BRANCH_OP_NEVER: taken_out = 0; - RV32_BRANCH_OP_ZERO: taken_out = ~non_zero; - RV32_BRANCH_OP_NON_ZERO: taken_out = non_zero; - RV32_BRANCH_OP_ALWAYS: taken_out = 1; + `RV32_BRANCH_OP_NEVER: taken_out = 0; + `RV32_BRANCH_OP_ZERO: taken_out = ~non_zero; + `RV32_BRANCH_OP_NON_ZERO: taken_out = non_zero; + `RV32_BRANCH_OP_ALWAYS: taken_out = 1; endcase end endmodule diff --git a/rv32_decode.sv b/rv32_decode.sv index 66caf95..7e5c5b2 100644 --- a/rv32_decode.sv +++ b/rv32_decode.sv @@ -103,7 +103,7 @@ module rv32_decode ( mem_write_out <= 0; mem_width_out <= 2'bx; mem_zero_extend_out <= 1'bx; - branch_op_out <= RV32_BRANCH_OP_NEVER; + branch_op_out <= `RV32_BRANCH_OP_NEVER; branch_pc_src_out <= 1'bx; rd_out <= rd; rd_write_out <= 0; @@ -112,384 +112,384 @@ module rv32_decode ( imm_out <= 32'bx; casez ({opcode, funct3, funct7}) - {RV32_OPCODE_LUI, RV32_FUNCT3_ANY, RV32_FUNCT7_ANY}: begin + {`RV32_OPCODE_LUI, `RV32_FUNCT3_ANY, `RV32_FUNCT7_ANY}: begin /* LUI */ valid_out <= 1; - alu_op_out <= RV32_ALU_OP_SRC2; - alu_src2_out <= RV32_ALU_SRC2_IMM; + alu_op_out <= `RV32_ALU_OP_SRC2; + alu_src2_out <= `RV32_ALU_SRC2_IMM; rd_write_out <= 1; imm_out <= imm_u; end - {RV32_OPCODE_AUIPC, RV32_FUNCT3_ANY, RV32_FUNCT7_ANY}: begin + {`RV32_OPCODE_AUIPC, `RV32_FUNCT3_ANY, `RV32_FUNCT7_ANY}: begin /* AUIPC */ valid_out <= 1; - alu_op_out <= RV32_ALU_OP_ADD_SUB; + alu_op_out <= `RV32_ALU_OP_ADD_SUB; alu_sub_sra_out <= 0; - alu_src1_out <= RV32_ALU_SRC1_PC; - alu_src2_out <= RV32_ALU_SRC2_IMM; + alu_src1_out <= `RV32_ALU_SRC1_PC; + alu_src2_out <= `RV32_ALU_SRC2_IMM; rd_write_out <= 1; imm_out <= imm_u; end - {RV32_OPCODE_JAL, RV32_FUNCT3_ANY, RV32_FUNCT7_ANY}: begin + {`RV32_OPCODE_JAL, `RV32_FUNCT3_ANY, `RV32_FUNCT7_ANY}: begin /* JAL */ valid_out <= 1; - alu_op_out <= RV32_ALU_OP_SRC1P4; - alu_src1_out <= RV32_ALU_SRC1_PC; - branch_op_out <= RV32_BRANCH_OP_ALWAYS; - branch_pc_src_out <= RV32_BRANCH_PC_SRC_IMM; + alu_op_out <= `RV32_ALU_OP_SRC1P4; + alu_src1_out <= `RV32_ALU_SRC1_PC; + branch_op_out <= `RV32_BRANCH_OP_ALWAYS; + branch_pc_src_out <= `RV32_BRANCH_PC_SRC_IMM; rd_write_out <= 1; imm_out <= imm_j; end - {RV32_OPCODE_JALR, RV32_FUNCT3_ZERO, RV32_FUNCT7_ANY}: begin + {`RV32_OPCODE_JALR, `RV32_FUNCT3_ZERO, `RV32_FUNCT7_ANY}: begin /* JALR */ valid_out <= 1; - alu_op_out <= RV32_ALU_OP_SRC1P4; - alu_src1_out <= RV32_ALU_SRC1_PC; - branch_op_out <= RV32_BRANCH_OP_ALWAYS; - branch_pc_src_out <= RV32_BRANCH_PC_SRC_REG; + alu_op_out <= `RV32_ALU_OP_SRC1P4; + alu_src1_out <= `RV32_ALU_SRC1_PC; + branch_op_out <= `RV32_BRANCH_OP_ALWAYS; + branch_pc_src_out <= `RV32_BRANCH_PC_SRC_REG; rd_write_out <= 1; imm_out <= imm_i; end - {RV32_OPCODE_BRANCH, RV32_FUNCT3_BRANCH_BEQ, RV32_FUNCT7_ANY}: begin + {`RV32_OPCODE_BRANCH, `RV32_FUNCT3_BRANCH_BEQ, `RV32_FUNCT7_ANY}: begin /* BEQ */ valid_out <= 1; - alu_op_out <= RV32_ALU_OP_ADD_SUB; + alu_op_out <= `RV32_ALU_OP_ADD_SUB; alu_sub_sra_out <= 1; - alu_src1_out <= RV32_ALU_SRC1_REG; - alu_src2_out <= RV32_ALU_SRC2_REG; - branch_op_out <= RV32_BRANCH_OP_ZERO; - branch_pc_src_out <= RV32_BRANCH_PC_SRC_IMM; + alu_src1_out <= `RV32_ALU_SRC1_REG; + alu_src2_out <= `RV32_ALU_SRC2_REG; + branch_op_out <= `RV32_BRANCH_OP_ZERO; + branch_pc_src_out <= `RV32_BRANCH_PC_SRC_IMM; imm_out <= imm_b; end - {RV32_OPCODE_BRANCH, RV32_FUNCT3_BRANCH_BNE, RV32_FUNCT7_ANY}: begin + {`RV32_OPCODE_BRANCH, `RV32_FUNCT3_BRANCH_BNE, `RV32_FUNCT7_ANY}: begin /* BNE */ valid_out <= 1; - alu_op_out <= RV32_ALU_OP_ADD_SUB; + alu_op_out <= `RV32_ALU_OP_ADD_SUB; alu_sub_sra_out <= 1; - alu_src1_out <= RV32_ALU_SRC1_REG; - alu_src2_out <= RV32_ALU_SRC2_REG; - branch_op_out <= RV32_BRANCH_OP_NON_ZERO; - branch_pc_src_out <= RV32_BRANCH_PC_SRC_IMM; + alu_src1_out <= `RV32_ALU_SRC1_REG; + alu_src2_out <= `RV32_ALU_SRC2_REG; + branch_op_out <= `RV32_BRANCH_OP_NON_ZERO; + branch_pc_src_out <= `RV32_BRANCH_PC_SRC_IMM; imm_out <= imm_b; end - {RV32_OPCODE_BRANCH, RV32_FUNCT3_BRANCH_BLT, RV32_FUNCT7_ANY}: begin + {`RV32_OPCODE_BRANCH, `RV32_FUNCT3_BRANCH_BLT, `RV32_FUNCT7_ANY}: begin /* BLT */ valid_out <= 1; - alu_op_out <= RV32_ALU_OP_SLT; + alu_op_out <= `RV32_ALU_OP_SLT; alu_sub_sra_out <= 1; - alu_src1_out <= RV32_ALU_SRC1_REG; - alu_src2_out <= RV32_ALU_SRC2_REG; - branch_op_out <= RV32_BRANCH_OP_NON_ZERO; - branch_pc_src_out <= RV32_BRANCH_PC_SRC_IMM; + alu_src1_out <= `RV32_ALU_SRC1_REG; + alu_src2_out <= `RV32_ALU_SRC2_REG; + branch_op_out <= `RV32_BRANCH_OP_NON_ZERO; + branch_pc_src_out <= `RV32_BRANCH_PC_SRC_IMM; imm_out <= imm_b; end - {RV32_OPCODE_BRANCH, RV32_FUNCT3_BRANCH_BGE, RV32_FUNCT7_ANY}: begin + {`RV32_OPCODE_BRANCH, `RV32_FUNCT3_BRANCH_BGE, `RV32_FUNCT7_ANY}: begin /* BGE */ valid_out <= 1; - alu_op_out <= RV32_ALU_OP_SLT; + alu_op_out <= `RV32_ALU_OP_SLT; alu_sub_sra_out <= 1; - alu_src1_out <= RV32_ALU_SRC1_REG; - alu_src2_out <= RV32_ALU_SRC2_REG; - branch_op_out <= RV32_BRANCH_OP_ZERO; - branch_pc_src_out <= RV32_BRANCH_PC_SRC_IMM; + alu_src1_out <= `RV32_ALU_SRC1_REG; + alu_src2_out <= `RV32_ALU_SRC2_REG; + branch_op_out <= `RV32_BRANCH_OP_ZERO; + branch_pc_src_out <= `RV32_BRANCH_PC_SRC_IMM; imm_out <= imm_b; end - {RV32_OPCODE_BRANCH, RV32_FUNCT3_BRANCH_BLTU, RV32_FUNCT7_ANY}: begin + {`RV32_OPCODE_BRANCH, `RV32_FUNCT3_BRANCH_BLTU, `RV32_FUNCT7_ANY}: begin /* BLTU */ valid_out <= 1; - alu_op_out <= RV32_ALU_OP_SLTU; + alu_op_out <= `RV32_ALU_OP_SLTU; alu_sub_sra_out <= 1; - alu_src1_out <= RV32_ALU_SRC1_REG; - alu_src2_out <= RV32_ALU_SRC2_REG; - branch_op_out <= RV32_BRANCH_OP_NON_ZERO; - branch_pc_src_out <= RV32_BRANCH_PC_SRC_IMM; + alu_src1_out <= `RV32_ALU_SRC1_REG; + alu_src2_out <= `RV32_ALU_SRC2_REG; + branch_op_out <= `RV32_BRANCH_OP_NON_ZERO; + branch_pc_src_out <= `RV32_BRANCH_PC_SRC_IMM; imm_out <= imm_b; end - {RV32_OPCODE_BRANCH, RV32_FUNCT3_BRANCH_BGEU, RV32_FUNCT7_ANY}: begin + {`RV32_OPCODE_BRANCH, `RV32_FUNCT3_BRANCH_BGEU, `RV32_FUNCT7_ANY}: begin /* BGEU */ valid_out <= 1; - alu_op_out <= RV32_ALU_OP_SLTU; + alu_op_out <= `RV32_ALU_OP_SLTU; alu_sub_sra_out <= 1; - alu_src1_out <= RV32_ALU_SRC1_REG; - alu_src2_out <= RV32_ALU_SRC2_REG; - branch_op_out <= RV32_BRANCH_OP_ZERO; - branch_pc_src_out <= RV32_BRANCH_PC_SRC_IMM; + alu_src1_out <= `RV32_ALU_SRC1_REG; + alu_src2_out <= `RV32_ALU_SRC2_REG; + branch_op_out <= `RV32_BRANCH_OP_ZERO; + branch_pc_src_out <= `RV32_BRANCH_PC_SRC_IMM; imm_out <= imm_b; end - {RV32_OPCODE_LOAD, RV32_FUNCT3_LOAD_LB, RV32_FUNCT7_ANY}: begin + {`RV32_OPCODE_LOAD, `RV32_FUNCT3_LOAD_LB, `RV32_FUNCT7_ANY}: begin /* LB */ valid_out <= 1; - alu_op_out <= RV32_ALU_OP_ADD_SUB; + alu_op_out <= `RV32_ALU_OP_ADD_SUB; alu_sub_sra_out <= 0; - alu_src1_out <= RV32_ALU_SRC1_REG; - alu_src2_out <= RV32_ALU_SRC2_IMM; + alu_src1_out <= `RV32_ALU_SRC1_REG; + alu_src2_out <= `RV32_ALU_SRC2_IMM; mem_read_out <= 1; - mem_width_out <= RV32_MEM_WIDTH_BYTE; + mem_width_out <= `RV32_MEM_WIDTH_BYTE; mem_zero_extend_out <= 0; rd_write_out <= 1; imm_out <= imm_i; end - {RV32_OPCODE_LOAD, RV32_FUNCT3_LOAD_LH, RV32_FUNCT7_ANY}: begin + {`RV32_OPCODE_LOAD, `RV32_FUNCT3_LOAD_LH, `RV32_FUNCT7_ANY}: begin /* LH */ valid_out <= 1; - alu_op_out <= RV32_ALU_OP_ADD_SUB; + alu_op_out <= `RV32_ALU_OP_ADD_SUB; alu_sub_sra_out <= 0; - alu_src1_out <= RV32_ALU_SRC1_REG; - alu_src2_out <= RV32_ALU_SRC2_IMM; + alu_src1_out <= `RV32_ALU_SRC1_REG; + alu_src2_out <= `RV32_ALU_SRC2_IMM; mem_read_out <= 1; - mem_width_out <= RV32_MEM_WIDTH_HALF; + mem_width_out <= `RV32_MEM_WIDTH_HALF; mem_zero_extend_out <= 0; rd_write_out <= 1; imm_out <= imm_i; end - {RV32_OPCODE_LOAD, RV32_FUNCT3_LOAD_LW, RV32_FUNCT7_ANY}: begin + {`RV32_OPCODE_LOAD, `RV32_FUNCT3_LOAD_LW, `RV32_FUNCT7_ANY}: begin /* LW */ valid_out <= 1; - alu_op_out <= RV32_ALU_OP_ADD_SUB; + alu_op_out <= `RV32_ALU_OP_ADD_SUB; alu_sub_sra_out <= 0; - alu_src1_out <= RV32_ALU_SRC1_REG; - alu_src2_out <= RV32_ALU_SRC2_IMM; + alu_src1_out <= `RV32_ALU_SRC1_REG; + alu_src2_out <= `RV32_ALU_SRC2_IMM; mem_read_out <= 1; - mem_width_out <= RV32_MEM_WIDTH_WORD; + mem_width_out <= `RV32_MEM_WIDTH_WORD; rd_write_out <= 1; imm_out <= imm_i; end - {RV32_OPCODE_LOAD, RV32_FUNCT3_LOAD_LBU, RV32_FUNCT7_ANY}: begin + {`RV32_OPCODE_LOAD, `RV32_FUNCT3_LOAD_LBU, `RV32_FUNCT7_ANY}: begin /* LBU */ valid_out <= 1; - alu_op_out <= RV32_ALU_OP_ADD_SUB; + alu_op_out <= `RV32_ALU_OP_ADD_SUB; alu_sub_sra_out <= 0; - alu_src1_out <= RV32_ALU_SRC1_REG; - alu_src2_out <= RV32_ALU_SRC2_IMM; + alu_src1_out <= `RV32_ALU_SRC1_REG; + alu_src2_out <= `RV32_ALU_SRC2_IMM; mem_read_out <= 1; - mem_width_out <= RV32_MEM_WIDTH_BYTE; + mem_width_out <= `RV32_MEM_WIDTH_BYTE; mem_zero_extend_out <= 1; rd_write_out <= 1; imm_out <= imm_i; end - {RV32_OPCODE_LOAD, RV32_FUNCT3_LOAD_LHU, RV32_FUNCT7_ANY}: begin + {`RV32_OPCODE_LOAD, `RV32_FUNCT3_LOAD_LHU, `RV32_FUNCT7_ANY}: begin /* LHU */ valid_out <= 1; - alu_op_out <= RV32_ALU_OP_ADD_SUB; + alu_op_out <= `RV32_ALU_OP_ADD_SUB; alu_sub_sra_out <= 0; - alu_src1_out <= RV32_ALU_SRC1_REG; - alu_src2_out <= RV32_ALU_SRC2_IMM; + alu_src1_out <= `RV32_ALU_SRC1_REG; + alu_src2_out <= `RV32_ALU_SRC2_IMM; mem_read_out <= 1; - mem_width_out <= RV32_MEM_WIDTH_HALF; + mem_width_out <= `RV32_MEM_WIDTH_HALF; mem_zero_extend_out <= 1; rd_write_out <= 1; imm_out <= imm_i; end - {RV32_OPCODE_STORE, RV32_FUNCT3_STORE_SB, RV32_FUNCT7_ANY}: begin + {`RV32_OPCODE_STORE, `RV32_FUNCT3_STORE_SB, `RV32_FUNCT7_ANY}: begin /* SB */ valid_out <= 1; - alu_op_out <= RV32_ALU_OP_ADD_SUB; + alu_op_out <= `RV32_ALU_OP_ADD_SUB; alu_sub_sra_out <= 0; - alu_src1_out <= RV32_ALU_SRC1_REG; - alu_src2_out <= RV32_ALU_SRC2_IMM; + alu_src1_out <= `RV32_ALU_SRC1_REG; + alu_src2_out <= `RV32_ALU_SRC2_IMM; mem_write_out <= 1; - mem_width_out <= RV32_MEM_WIDTH_BYTE; + mem_width_out <= `RV32_MEM_WIDTH_BYTE; imm_out <= imm_s; end - {RV32_OPCODE_STORE, RV32_FUNCT3_STORE_SH, RV32_FUNCT7_ANY}: begin + {`RV32_OPCODE_STORE, `RV32_FUNCT3_STORE_SH, `RV32_FUNCT7_ANY}: begin /* SH */ valid_out <= 1; - alu_op_out <= RV32_ALU_OP_ADD_SUB; + alu_op_out <= `RV32_ALU_OP_ADD_SUB; alu_sub_sra_out <= 0; - alu_src1_out <= RV32_ALU_SRC1_REG; - alu_src2_out <= RV32_ALU_SRC2_IMM; + alu_src1_out <= `RV32_ALU_SRC1_REG; + alu_src2_out <= `RV32_ALU_SRC2_IMM; mem_write_out <= 1; - mem_width_out <= RV32_MEM_WIDTH_HALF; + mem_width_out <= `RV32_MEM_WIDTH_HALF; imm_out <= imm_s; end - {RV32_OPCODE_STORE, RV32_FUNCT3_STORE_SW, RV32_FUNCT7_ANY}: begin + {`RV32_OPCODE_STORE, `RV32_FUNCT3_STORE_SW, `RV32_FUNCT7_ANY}: begin /* SW */ valid_out <= 1; - alu_op_out <= RV32_ALU_OP_ADD_SUB; + alu_op_out <= `RV32_ALU_OP_ADD_SUB; alu_sub_sra_out <= 0; - alu_src1_out <= RV32_ALU_SRC1_REG; - alu_src2_out <= RV32_ALU_SRC2_IMM; + alu_src1_out <= `RV32_ALU_SRC1_REG; + alu_src2_out <= `RV32_ALU_SRC2_IMM; mem_write_out <= 1; - mem_width_out <= RV32_MEM_WIDTH_WORD; + mem_width_out <= `RV32_MEM_WIDTH_WORD; imm_out <= imm_s; end - {RV32_OPCODE_OP_IMM, RV32_FUNCT3_OP_ADD_SUB, RV32_FUNCT7_ANY}: begin + {`RV32_OPCODE_OP_IMM, `RV32_FUNCT3_OP_ADD_SUB, `RV32_FUNCT7_ANY}: begin /* ADDI */ valid_out <= 1; - alu_op_out <= RV32_ALU_OP_ADD_SUB; + alu_op_out <= `RV32_ALU_OP_ADD_SUB; alu_sub_sra_out <= 0; - alu_src1_out <= RV32_ALU_SRC1_REG; - alu_src2_out <= RV32_ALU_SRC2_IMM; + alu_src1_out <= `RV32_ALU_SRC1_REG; + alu_src2_out <= `RV32_ALU_SRC2_IMM; rd_write_out <= 1; imm_out <= imm_i; end - {RV32_OPCODE_OP_IMM, RV32_FUNCT3_OP_SLT, RV32_FUNCT7_ANY}: begin + {`RV32_OPCODE_OP_IMM, `RV32_FUNCT3_OP_SLT, `RV32_FUNCT7_ANY}: begin /* SLTI */ valid_out <= 1; - alu_op_out <= RV32_ALU_OP_SLT; + alu_op_out <= `RV32_ALU_OP_SLT; alu_sub_sra_out <= 1; - alu_src1_out <= RV32_ALU_SRC1_REG; - alu_src2_out <= RV32_ALU_SRC2_IMM; + alu_src1_out <= `RV32_ALU_SRC1_REG; + alu_src2_out <= `RV32_ALU_SRC2_IMM; rd_write_out <= 1; imm_out <= imm_i; end - {RV32_OPCODE_OP_IMM, RV32_FUNCT3_OP_SLTU, RV32_FUNCT7_ANY}: begin + {`RV32_OPCODE_OP_IMM, `RV32_FUNCT3_OP_SLTU, `RV32_FUNCT7_ANY}: begin /* SLTIU */ valid_out <= 1; - alu_op_out <= RV32_ALU_OP_SLTU; + alu_op_out <= `RV32_ALU_OP_SLTU; alu_sub_sra_out <= 1; - alu_src1_out <= RV32_ALU_SRC1_REG; - alu_src2_out <= RV32_ALU_SRC2_IMM; + alu_src1_out <= `RV32_ALU_SRC1_REG; + alu_src2_out <= `RV32_ALU_SRC2_IMM; rd_write_out <= 1; imm_out <= imm_i; end - {RV32_OPCODE_OP_IMM, RV32_FUNCT3_OP_XOR, RV32_FUNCT7_ANY}: begin + {`RV32_OPCODE_OP_IMM, `RV32_FUNCT3_OP_XOR, `RV32_FUNCT7_ANY}: begin /* XORI */ valid_out <= 1; - alu_op_out <= RV32_ALU_OP_XOR; - alu_src1_out <= RV32_ALU_SRC1_REG; - alu_src2_out <= RV32_ALU_SRC2_IMM; + alu_op_out <= `RV32_ALU_OP_XOR; + alu_src1_out <= `RV32_ALU_SRC1_REG; + alu_src2_out <= `RV32_ALU_SRC2_IMM; rd_write_out <= 1; imm_out <= imm_i; end - {RV32_OPCODE_OP_IMM, RV32_FUNCT3_OP_OR, RV32_FUNCT7_ANY}: begin + {`RV32_OPCODE_OP_IMM, `RV32_FUNCT3_OP_OR, `RV32_FUNCT7_ANY}: begin /* ORI */ valid_out <= 1; - alu_op_out <= RV32_ALU_OP_OR; - alu_src1_out <= RV32_ALU_SRC1_REG; - alu_src2_out <= RV32_ALU_SRC2_IMM; + alu_op_out <= `RV32_ALU_OP_OR; + alu_src1_out <= `RV32_ALU_SRC1_REG; + alu_src2_out <= `RV32_ALU_SRC2_IMM; rd_write_out <= 1; imm_out <= imm_i; end - {RV32_OPCODE_OP_IMM, RV32_FUNCT3_OP_AND, RV32_FUNCT7_ANY}: begin + {`RV32_OPCODE_OP_IMM, `RV32_FUNCT3_OP_AND, `RV32_FUNCT7_ANY}: begin /* ANDI */ valid_out <= 1; - alu_op_out <= RV32_ALU_OP_AND; - alu_src1_out <= RV32_ALU_SRC1_REG; - alu_src2_out <= RV32_ALU_SRC2_IMM; + alu_op_out <= `RV32_ALU_OP_AND; + alu_src1_out <= `RV32_ALU_SRC1_REG; + alu_src2_out <= `RV32_ALU_SRC2_IMM; rd_write_out <= 1; imm_out <= imm_i; end - {RV32_OPCODE_OP_IMM, RV32_FUNCT3_OP_SLL, RV32_FUNCT7_ZERO}: begin + {`RV32_OPCODE_OP_IMM, `RV32_FUNCT3_OP_SLL, `RV32_FUNCT7_ZERO}: begin /* SLLI */ valid_out <= 1; - alu_op_out <= RV32_ALU_OP_SLL; - alu_src1_out <= RV32_ALU_SRC1_REG; - alu_src2_out <= RV32_ALU_SRC2_IMM; + alu_op_out <= `RV32_ALU_OP_SLL; + alu_src1_out <= `RV32_ALU_SRC1_REG; + alu_src2_out <= `RV32_ALU_SRC2_IMM; rd_write_out <= 1; imm_out <= shamt; end - {RV32_OPCODE_OP_IMM, RV32_FUNCT3_OP_SRL_SRA, RV32_FUNCT7_ZERO}: begin + {`RV32_OPCODE_OP_IMM, `RV32_FUNCT3_OP_SRL_SRA, `RV32_FUNCT7_ZERO}: begin /* SRLI */ valid_out <= 1; - alu_op_out <= RV32_ALU_OP_SRL_SRA; + alu_op_out <= `RV32_ALU_OP_SRL_SRA; alu_sub_sra_out <= 0; - alu_src1_out <= RV32_ALU_SRC1_REG; - alu_src2_out <= RV32_ALU_SRC2_IMM; + alu_src1_out <= `RV32_ALU_SRC1_REG; + alu_src2_out <= `RV32_ALU_SRC2_IMM; rd_write_out <= 1; imm_out <= shamt; end - {RV32_OPCODE_OP_IMM, RV32_FUNCT3_OP_SRL_SRA, RV32_FUNCT7_OP_SRA}: begin + {`RV32_OPCODE_OP_IMM, `RV32_FUNCT3_OP_SRL_SRA, `RV32_FUNCT7_OP_SRA}: begin /* SRAI */ valid_out <= 1; - alu_op_out <= RV32_ALU_OP_SRL_SRA; + alu_op_out <= `RV32_ALU_OP_SRL_SRA; alu_sub_sra_out <= 1; - alu_src1_out <= RV32_ALU_SRC1_REG; - alu_src2_out <= RV32_ALU_SRC2_IMM; + alu_src1_out <= `RV32_ALU_SRC1_REG; + alu_src2_out <= `RV32_ALU_SRC2_IMM; rd_write_out <= 1; imm_out <= shamt; end - {RV32_OPCODE_OP, RV32_FUNCT3_OP_ADD_SUB, RV32_FUNCT7_ZERO}: begin + {`RV32_OPCODE_OP, `RV32_FUNCT3_OP_ADD_SUB, `RV32_FUNCT7_ZERO}: begin /* ADD */ valid_out <= 1; - alu_op_out <= RV32_ALU_OP_ADD_SUB; + alu_op_out <= `RV32_ALU_OP_ADD_SUB; alu_sub_sra_out <= 0; - alu_src1_out <= RV32_ALU_SRC1_REG; - alu_src2_out <= RV32_ALU_SRC2_REG; + alu_src1_out <= `RV32_ALU_SRC1_REG; + alu_src2_out <= `RV32_ALU_SRC2_REG; rd_write_out <= 1; end - {RV32_OPCODE_OP, RV32_FUNCT3_OP_ADD_SUB, RV32_FUNCT7_OP_SUB}: begin + {`RV32_OPCODE_OP, `RV32_FUNCT3_OP_ADD_SUB, `RV32_FUNCT7_OP_SUB}: begin /* SUB */ valid_out <= 1; - alu_op_out <= RV32_ALU_OP_ADD_SUB; + alu_op_out <= `RV32_ALU_OP_ADD_SUB; alu_sub_sra_out <= 1; - alu_src1_out <= RV32_ALU_SRC1_REG; - alu_src2_out <= RV32_ALU_SRC2_REG; + alu_src1_out <= `RV32_ALU_SRC1_REG; + alu_src2_out <= `RV32_ALU_SRC2_REG; rd_write_out <= 1; end - {RV32_OPCODE_OP, RV32_FUNCT3_OP_SLL, RV32_FUNCT7_ZERO}: begin + {`RV32_OPCODE_OP, `RV32_FUNCT3_OP_SLL, `RV32_FUNCT7_ZERO}: begin /* SLL */ valid_out <= 1; - alu_op_out <= RV32_ALU_OP_SLL; - alu_src1_out <= RV32_ALU_SRC1_REG; - alu_src2_out <= RV32_ALU_SRC2_REG; + alu_op_out <= `RV32_ALU_OP_SLL; + alu_src1_out <= `RV32_ALU_SRC1_REG; + alu_src2_out <= `RV32_ALU_SRC2_REG; rd_write_out <= 1; end - {RV32_OPCODE_OP, RV32_FUNCT3_OP_SLT, RV32_FUNCT7_ZERO}: begin + {`RV32_OPCODE_OP, `RV32_FUNCT3_OP_SLT, `RV32_FUNCT7_ZERO}: begin /* SLT */ valid_out <= 1; - alu_op_out <= RV32_ALU_OP_SLT; + alu_op_out <= `RV32_ALU_OP_SLT; alu_sub_sra_out <= 1; - alu_src1_out <= RV32_ALU_SRC1_REG; - alu_src2_out <= RV32_ALU_SRC2_REG; + alu_src1_out <= `RV32_ALU_SRC1_REG; + alu_src2_out <= `RV32_ALU_SRC2_REG; rd_write_out <= 1; end - {RV32_OPCODE_OP, RV32_FUNCT3_OP_SLTU, RV32_FUNCT7_ZERO}: begin + {`RV32_OPCODE_OP, `RV32_FUNCT3_OP_SLTU, `RV32_FUNCT7_ZERO}: begin /* SLTU */ valid_out <= 1; - alu_op_out <= RV32_ALU_OP_SLTU; + alu_op_out <= `RV32_ALU_OP_SLTU; alu_sub_sra_out <= 1; - alu_src1_out <= RV32_ALU_SRC1_REG; - alu_src2_out <= RV32_ALU_SRC2_REG; + alu_src1_out <= `RV32_ALU_SRC1_REG; + alu_src2_out <= `RV32_ALU_SRC2_REG; rd_write_out <= 1; end - {RV32_OPCODE_OP, RV32_FUNCT3_OP_XOR, RV32_FUNCT7_ZERO}: begin + {`RV32_OPCODE_OP, `RV32_FUNCT3_OP_XOR, `RV32_FUNCT7_ZERO}: begin /* XOR */ valid_out <= 1; - alu_op_out <= RV32_ALU_OP_XOR; - alu_src1_out <= RV32_ALU_SRC1_REG; - alu_src2_out <= RV32_ALU_SRC2_REG; + alu_op_out <= `RV32_ALU_OP_XOR; + alu_src1_out <= `RV32_ALU_SRC1_REG; + alu_src2_out <= `RV32_ALU_SRC2_REG; rd_write_out <= 1; end - {RV32_OPCODE_OP, RV32_FUNCT3_OP_SRL_SRA, RV32_FUNCT7_ZERO}: begin + {`RV32_OPCODE_OP, `RV32_FUNCT3_OP_SRL_SRA, `RV32_FUNCT7_ZERO}: begin /* SRL */ valid_out <= 1; - alu_op_out <= RV32_ALU_OP_SRL_SRA; + alu_op_out <= `RV32_ALU_OP_SRL_SRA; alu_sub_sra_out <= 0; - alu_src1_out <= RV32_ALU_SRC1_REG; - alu_src2_out <= RV32_ALU_SRC2_REG; + alu_src1_out <= `RV32_ALU_SRC1_REG; + alu_src2_out <= `RV32_ALU_SRC2_REG; rd_write_out <= 1; end - {RV32_OPCODE_OP, RV32_FUNCT3_OP_SRL_SRA, RV32_FUNCT7_OP_SRA}: begin + {`RV32_OPCODE_OP, `RV32_FUNCT3_OP_SRL_SRA, `RV32_FUNCT7_OP_SRA}: begin /* SRA */ valid_out <= 1; - alu_op_out <= RV32_ALU_OP_SRL_SRA; + alu_op_out <= `RV32_ALU_OP_SRL_SRA; alu_sub_sra_out <= 1; - alu_src1_out <= RV32_ALU_SRC1_REG; - alu_src2_out <= RV32_ALU_SRC2_REG; + alu_src1_out <= `RV32_ALU_SRC1_REG; + alu_src2_out <= `RV32_ALU_SRC2_REG; rd_write_out <= 1; end - {RV32_OPCODE_OP, RV32_FUNCT3_OP_OR, RV32_FUNCT7_ZERO}: begin + {`RV32_OPCODE_OP, `RV32_FUNCT3_OP_OR, `RV32_FUNCT7_ZERO}: begin /* OR */ valid_out <= 1; - alu_op_out <= RV32_ALU_OP_OR; - alu_src1_out <= RV32_ALU_SRC1_REG; - alu_src2_out <= RV32_ALU_SRC2_REG; + alu_op_out <= `RV32_ALU_OP_OR; + alu_src1_out <= `RV32_ALU_SRC1_REG; + alu_src2_out <= `RV32_ALU_SRC2_REG; rd_write_out <= 1; end - {RV32_OPCODE_OP, RV32_FUNCT3_OP_AND, RV32_FUNCT7_ZERO}: begin + {`RV32_OPCODE_OP, `RV32_FUNCT3_OP_AND, `RV32_FUNCT7_ZERO}: begin /* AND */ valid_out <= 1; - alu_op_out <= RV32_ALU_OP_AND; - alu_src1_out <= RV32_ALU_SRC1_REG; - alu_src2_out <= RV32_ALU_SRC2_REG; + alu_op_out <= `RV32_ALU_OP_AND; + alu_src1_out <= `RV32_ALU_SRC1_REG; + alu_src2_out <= `RV32_ALU_SRC2_REG; rd_write_out <= 1; end - {RV32_OPCODE_MISC_MEM, RV32_FUNCT3_MISC_MEM_FENCE, RV32_FUNCT7_ANY}: begin + {`RV32_OPCODE_MISC_MEM, `RV32_FUNCT3_MISC_MEM_FENCE, `RV32_FUNCT7_ANY}: begin /* FENCE */ valid_out <= 1; end - {RV32_OPCODE_MISC_MEM, RV32_FUNCT3_MISC_MEM_FENCE_I, RV32_FUNCT7_ANY}: begin + {`RV32_OPCODE_MISC_MEM, `RV32_FUNCT3_MISC_MEM_FENCE_I, `RV32_FUNCT7_ANY}: begin /* FENCE.I */ valid_out <= 1; end @@ -498,7 +498,7 @@ module rv32_decode ( if (flush_in) begin mem_read_out <= 0; mem_write_out <= 0; - branch_op_out <= RV32_BRANCH_OP_NEVER; + branch_op_out <= `RV32_BRANCH_OP_NEVER; rd_write_out <= 0; end end diff --git a/rv32_execute.sv b/rv32_execute.sv index 28cd747..8fd1dec 100644 --- a/rv32_execute.sv +++ b/rv32_execute.sv @@ -123,7 +123,7 @@ module rv32_execute ( if (flush_in) begin mem_read_out <= 0; mem_write_out <= 0; - branch_op_out <= RV32_BRANCH_OP_NEVER; + branch_op_out <= `RV32_BRANCH_OP_NEVER; rd_write_out <= 0; end end diff --git a/rv32_fetch.sv b/rv32_fetch.sv index 66c6b30..120794e 100644 --- a/rv32_fetch.sv +++ b/rv32_fetch.sv @@ -35,7 +35,7 @@ module rv32_fetch ( pc_out <= pc; if (flush_in) - instr_out <= RV32_INSTR_NOP; + instr_out <= `RV32_INSTR_NOP; end end endmodule diff --git a/rv32_mem.sv b/rv32_mem.sv index 564280c..4cd0e96 100644 --- a/rv32_mem.sv +++ b/rv32_mem.sv @@ -3,9 +3,9 @@ `include "rv32_branch.sv" -localparam RV32_MEM_WIDTH_WORD = 2'b00; -localparam RV32_MEM_WIDTH_HALF = 2'b01; -localparam RV32_MEM_WIDTH_BYTE = 2'b10; +`define RV32_MEM_WIDTH_WORD 2'b00 +`define RV32_MEM_WIDTH_HALF 2'b01 +`define RV32_MEM_WIDTH_BYTE 2'b10 module rv32_mem ( input clk, @@ -67,11 +67,11 @@ module rv32_mem ( always_comb begin if (write_in) begin case (width_in) - RV32_MEM_WIDTH_WORD: begin + `RV32_MEM_WIDTH_WORD: begin write_value_out = rs2_value_in; write_mask_out = 4'b1111; end - RV32_MEM_WIDTH_HALF: begin + `RV32_MEM_WIDTH_HALF: begin case (result_in[0]) 2'b0: begin write_value_out = {rs2_value_in[15:0], 16'bx}; @@ -83,7 +83,7 @@ module rv32_mem ( end endcase end - RV32_MEM_WIDTH_BYTE: begin + `RV32_MEM_WIDTH_BYTE: begin case (result_in[1:0]) 2'b00: begin write_value_out = {rs2_value_in[7:0], 24'bx}; @@ -121,16 +121,16 @@ module rv32_mem ( if (read_in) begin case (width_in) - RV32_MEM_WIDTH_WORD: begin + `RV32_MEM_WIDTH_WORD: begin rd_value_out <= read_value_in; end - RV32_MEM_WIDTH_HALF: begin + `RV32_MEM_WIDTH_HALF: begin case (result_in[0]) 1'b0: rd_value_out <= {{16{zero_extend_in ? 1'b0 : read_value_in[31]}}, read_value_in[31:16]}; 1'b1: rd_value_out <= {{16{zero_extend_in ? 1'b0 : read_value_in[15]}}, read_value_in[15:0]}; endcase end - RV32_MEM_WIDTH_BYTE: begin + `RV32_MEM_WIDTH_BYTE: begin case (result_in[1:0]) 2'b00: rd_value_out <= {{24{zero_extend_in ? 1'b0 : read_value_in[31]}}, read_value_in[31:24]}; 2'b01: rd_value_out <= {{24{zero_extend_in ? 1'b0 : read_value_in[23]}}, read_value_in[23:16]}; diff --git a/rv32_opcodes.sv b/rv32_opcodes.sv index e2298f7..ec83b24 100644 --- a/rv32_opcodes.sv +++ b/rv32_opcodes.sv @@ -1,56 +1,56 @@ `ifndef RV32_OPCODES `define RV32_OPCODES -localparam RV32_OPCODE_LOAD = 7'b0000011; -localparam RV32_OPCODE_MISC_MEM = 7'b0001111; -localparam RV32_OPCODE_OP_IMM = 7'b0010011; -localparam RV32_OPCODE_AUIPC = 7'b0010111; -localparam RV32_OPCODE_STORE = 7'b0100011; -localparam RV32_OPCODE_OP = 7'b0110011; -localparam RV32_OPCODE_LUI = 7'b0110111; -localparam RV32_OPCODE_BRANCH = 7'b1100011; -localparam RV32_OPCODE_JALR = 7'b1100111; -localparam RV32_OPCODE_JAL = 7'b1101111; -localparam RV32_OPCODE_SYSTEM = 7'b1110011; +`define RV32_OPCODE_LOAD 7'b0000011 +`define RV32_OPCODE_MISC_MEM 7'b0001111 +`define RV32_OPCODE_OP_IMM 7'b0010011 +`define RV32_OPCODE_AUIPC 7'b0010111 +`define RV32_OPCODE_STORE 7'b0100011 +`define RV32_OPCODE_OP 7'b0110011 +`define RV32_OPCODE_LUI 7'b0110111 +`define RV32_OPCODE_BRANCH 7'b1100011 +`define RV32_OPCODE_JALR 7'b1100111 +`define RV32_OPCODE_JAL 7'b1101111 +`define RV32_OPCODE_SYSTEM 7'b1110011 -localparam RV32_FUNCT3_ANY = 3'b???; -localparam RV32_FUNCT3_ZERO = 3'b000; +`define RV32_FUNCT3_ANY 3'b??? +`define RV32_FUNCT3_ZERO 3'b000 -localparam RV32_FUNCT3_BRANCH_BEQ = 3'b000; -localparam RV32_FUNCT3_BRANCH_BNE = 3'b001; -localparam RV32_FUNCT3_BRANCH_BLT = 3'b100; -localparam RV32_FUNCT3_BRANCH_BGE = 3'b101; -localparam RV32_FUNCT3_BRANCH_BLTU = 3'b110; -localparam RV32_FUNCT3_BRANCH_BGEU = 3'b111; +`define RV32_FUNCT3_BRANCH_BEQ 3'b000 +`define RV32_FUNCT3_BRANCH_BNE 3'b001 +`define RV32_FUNCT3_BRANCH_BLT 3'b100 +`define RV32_FUNCT3_BRANCH_BGE 3'b101 +`define RV32_FUNCT3_BRANCH_BLTU 3'b110 +`define RV32_FUNCT3_BRANCH_BGEU 3'b111 -localparam RV32_FUNCT3_LOAD_LB = 3'b000; -localparam RV32_FUNCT3_LOAD_LH = 3'b001; -localparam RV32_FUNCT3_LOAD_LW = 3'b010; -localparam RV32_FUNCT3_LOAD_LBU = 3'b100; -localparam RV32_FUNCT3_LOAD_LHU = 3'b101; +`define RV32_FUNCT3_LOAD_LB 3'b000 +`define RV32_FUNCT3_LOAD_LH 3'b001 +`define RV32_FUNCT3_LOAD_LW 3'b010 +`define RV32_FUNCT3_LOAD_LBU 3'b100 +`define RV32_FUNCT3_LOAD_LHU 3'b101 -localparam RV32_FUNCT3_STORE_SB = 3'b000; -localparam RV32_FUNCT3_STORE_SH = 3'b001; -localparam RV32_FUNCT3_STORE_SW = 3'b010; +`define RV32_FUNCT3_STORE_SB 3'b000 +`define RV32_FUNCT3_STORE_SH 3'b001 +`define RV32_FUNCT3_STORE_SW 3'b010 -localparam RV32_FUNCT3_OP_ADD_SUB = 3'b000; -localparam RV32_FUNCT3_OP_SLL = 3'b001; -localparam RV32_FUNCT3_OP_SLT = 3'b010; -localparam RV32_FUNCT3_OP_SLTU = 3'b011; -localparam RV32_FUNCT3_OP_XOR = 3'b100; -localparam RV32_FUNCT3_OP_SRL_SRA = 3'b101; -localparam RV32_FUNCT3_OP_OR = 3'b110; -localparam RV32_FUNCT3_OP_AND = 3'b111; +`define RV32_FUNCT3_OP_ADD_SUB 3'b000 +`define RV32_FUNCT3_OP_SLL 3'b001 +`define RV32_FUNCT3_OP_SLT 3'b010 +`define RV32_FUNCT3_OP_SLTU 3'b011 +`define RV32_FUNCT3_OP_XOR 3'b100 +`define RV32_FUNCT3_OP_SRL_SRA 3'b101 +`define RV32_FUNCT3_OP_OR 3'b110 +`define RV32_FUNCT3_OP_AND 3'b111 -localparam RV32_FUNCT3_MISC_MEM_FENCE = 3'b000; -localparam RV32_FUNCT3_MISC_MEM_FENCE_I = 3'b001; +`define RV32_FUNCT3_MISC_MEM_FENCE 3'b000 +`define RV32_FUNCT3_MISC_MEM_FENCE_I 3'b001 -localparam RV32_FUNCT7_ANY = 7'b???????; -localparam RV32_FUNCT7_ZERO = 7'b0000000; +`define RV32_FUNCT7_ANY 7'b??????? +`define RV32_FUNCT7_ZERO 7'b0000000 -localparam RV32_FUNCT7_OP_SRA = 7'b0100000; -localparam RV32_FUNCT7_OP_SUB = 7'b0100000; +`define RV32_FUNCT7_OP_SRA 7'b0100000 +`define RV32_FUNCT7_OP_SUB 7'b0100000 -localparam RV32_INSTR_NOP = {12'bx, 5'b0, 3'bx, 5'b0, RV32_OPCODE_OP_IMM}; +`define RV32_INSTR_NOP {12'bx, 5'b0, 3'bx, 5'b0, `RV32_OPCODE_OP_IMM} `endif diff --git a/uart.sv b/uart.sv index cbe1539..eb08ec8 100644 --- a/uart.sv +++ b/uart.sv @@ -1,9 +1,9 @@ `ifndef UART `define UART -localparam UART_REG_CLK_DIV = 2'b00; -localparam UART_REG_STATUS = 2'b01; -localparam UART_REG_DATA = 2'b10; +`define UART_REG_CLK_DIV 2'b00 +`define UART_REG_STATUS 2'b01 +`define UART_REG_DATA 2'b10 module uart ( input clk, @@ -48,13 +48,13 @@ module uart ( always_comb begin if (sel_in) begin case (address_in[3:2]) - UART_REG_CLK_DIV: begin + `UART_REG_CLK_DIV: begin read_value_out = {16'b0, clk_div}; end - UART_REG_STATUS: begin + `UART_REG_STATUS: begin read_value_out = {30'b0, rx_read_ready, tx_write_ready}; end - UART_REG_DATA: begin + `UART_REG_DATA: begin read_value_out = {{24{~rx_read_ready}}, rx_read_ready ? rx_read_buf : 8'b0}; end default: begin @@ -69,14 +69,14 @@ module uart ( always_ff @(posedge clk) begin if (sel_in) begin case (address_in[3:2]) - UART_REG_CLK_DIV: begin + `UART_REG_CLK_DIV: begin if (write_mask_in[1]) clk_div[15:8] <= write_value_in[15:8]; if (write_mask_in[0]) clk_div[7:0] <= write_value_in[7:0]; end - UART_REG_DATA: begin + `UART_REG_DATA: begin if (read_in) rx_read_ready <= 0;