diff --git a/rv32.sv b/rv32.sv
index db79ab7..214d6c9 100644
--- a/rv32.sv
+++ b/rv32.sv
@@ -1,3 +1,6 @@
+`ifndef RV32
+`define RV32
+
 `include "rv32_decode.sv"
 `include "rv32_execute.sv"
 `include "rv32_fetch.sv"
@@ -71,3 +74,5 @@ module rv32 (
     /* execute -> mem data */
     logic [31:0] execute_result;
 endmodule
+
+`endif
diff --git a/rv32_alu.sv b/rv32_alu.sv
index beefbcb..92313fd 100644
--- a/rv32_alu.sv
+++ b/rv32_alu.sv
@@ -1,3 +1,6 @@
+`ifndef RV32_ALU
+`define RV32_ALU
+
 `include "rv32_alu_ops.sv"
 
 module rv32_alu (
@@ -52,3 +55,5 @@ module rv32_alu (
         endcase
     end
 endmodule
+
+`endif
diff --git a/rv32_alu_ops.sv b/rv32_alu_ops.sv
index 2afb676..163bc7b 100644
--- a/rv32_alu_ops.sv
+++ b/rv32_alu_ops.sv
@@ -1,3 +1,6 @@
+`ifndef RV32_ALU_OPS
+`define RV32_ALU_OPS
+
 localparam RV32_ALU_OP_ADD_SUB = 4'b0000;
 localparam RV32_ALU_OP_XOR     = 4'b0001;
 localparam RV32_ALU_OP_OR      = 4'b0010;
@@ -14,3 +17,5 @@ localparam RV32_ALU_SRC1_PC  = 1'b1;
 
 localparam RV32_ALU_SRC2_REG = 1'b0;
 localparam RV32_ALU_SRC2_IMM = 1'b1;
+
+`endif
diff --git a/rv32_decode.sv b/rv32_decode.sv
index be68be0..b81b24e 100644
--- a/rv32_decode.sv
+++ b/rv32_decode.sv
@@ -1,3 +1,6 @@
+`ifndef RV32_DECODE
+`define RV32_DECODE
+
 `include "rv32_alu_ops.sv"
 `include "rv32_opcodes.sv"
 `include "rv32_regs.sv"
@@ -374,3 +377,5 @@ module rv32_decode (
         endcase
     end
 endmodule
+
+`endif
diff --git a/rv32_execute.sv b/rv32_execute.sv
index 0d471e4..a2cbc4c 100644
--- a/rv32_execute.sv
+++ b/rv32_execute.sv
@@ -1,3 +1,6 @@
+`ifndef RV32_EXECUTE
+`define RV32_EXECUTE
+
 `include "rv32_alu.sv"
 
 module rv32_execute (
@@ -37,3 +40,5 @@ module rv32_execute (
         .result_out(result_out)
     );
 endmodule
+
+`endif
diff --git a/rv32_fetch.sv b/rv32_fetch.sv
index a79fe6e..fde1407 100644
--- a/rv32_fetch.sv
+++ b/rv32_fetch.sv
@@ -1,3 +1,6 @@
+`ifndef RV32_FETCH
+`define RV32_FETCH
+
 module rv32_fetch (
     input clk,
 
@@ -14,3 +17,5 @@ module rv32_fetch (
         pc_out <= pc;
     end
 endmodule
+
+`endif
diff --git a/rv32_opcodes.sv b/rv32_opcodes.sv
index 5dd1ebb..ef6dd25 100644
--- a/rv32_opcodes.sv
+++ b/rv32_opcodes.sv
@@ -1,3 +1,6 @@
+`ifndef RV32_OPCODES
+`define RV32_OPCODES
+
 localparam RV32_OPCODE_LOAD     = 7'b0000011;
 localparam RV32_OPCODE_MISC_MEM = 7'b0001111;
 localparam RV32_OPCODE_OP_IMM   = 7'b0010011;
@@ -44,3 +47,5 @@ localparam RV32_FUNCT7_ZERO = 7'b0000000;
 
 localparam RV32_FUNCT7_OP_SRA = 7'b0100000;
 localparam RV32_FUNCT7_OP_SUB = 7'b0100000;
+
+`endif
diff --git a/rv32_regs.sv b/rv32_regs.sv
index 69a7bc9..f2d3b12 100644
--- a/rv32_regs.sv
+++ b/rv32_regs.sv
@@ -1,3 +1,6 @@
+`ifndef RV32_REGS
+`define RV32_REGS
+
 module rv32_regs (
     input clk,
 
@@ -24,3 +27,5 @@ module rv32_regs (
             regs[rd_in] <= rd_value_in;
     end
 endmodule
+
+`endif