40 lines
772 B
Systemverilog
40 lines
772 B
Systemverilog
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`include "rv32_alu.sv"
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module rv32_execute (
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input clk,
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/* control in */
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input [3:0] alu_op_in,
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input alu_sub_sra_in,
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input alu_src1_in,
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input alu_src2_in,
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/* data in */
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input [31:0] pc_in,
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input [31:0] rs1_value_in,
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input [31:0] rs2_value_in,
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input [31:0] imm_in,
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/* data out */
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output [31:0] result_out
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);
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rv32_alu alu (
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.clk(clk),
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/* control in */
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.op_in(alu_op_in),
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.sub_sra_in(alu_sub_sra_in),
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.src1_in(alu_src1_in),
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.src2_in(alu_src2_in),
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/* data in */
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.pc_in(pc_in),
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.rs1_value_in(rs1_value_in),
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.rs2_value_in(rs2_value_in),
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.imm_in(imm_in),
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/* data out */
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.result_out(result_out)
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);
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endmodule
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