32-bit RISC-V system on chip for iCE40 FPGAs

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Andrea Venturi 5c3487be49 add PCF file for UP5K part on upduino		2018-01-23 19:47:28 +01:00
.gitignore	Port example program to C	2017-12-15 20:08:55 +00:00
.gitlab-ci.yml	Add yosys-config --datdir workaround	2017-12-15 18:35:26 +00:00
bus_arbiter.sv	Combine the instruction and data buses	2017-12-25 23:33:53 +00:00
clk_div.sv	Fix compatibility with iverilog	2017-12-09 21:03:45 +00:00
ice40hx8k-b-evn.pcf	Add serial flash, LED and UART pins	2017-12-01 23:25:06 +00:00
ice40up5k-upduino.pcf	add PCF file for UP5K part on upduino	2018-01-23 19:47:28 +01:00
LICENSE	Add README and LICENSE	2018-01-04 22:48:30 +00:00
Makefile	support up5k FPGA with internal OSC	2018-01-23 18:17:44 +01:00
progmem.c	Add BAUD_RATE constant	2018-01-01 14:39:05 +00:00
progmem.lds	Add rodata to the linker script	2017-12-25 23:42:32 +00:00
ram.sv	Swap byte order in the ram module	2017-12-26 14:15:12 +00:00
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rv32.sv	Move result zero/non-zero test to the execute stage	2017-12-30 14:12:23 +00:00
rv32_alu.sv	Move result zero/non-zero test to the execute stage	2017-12-30 14:12:23 +00:00
rv32_branch.sv	Move result zero/non-zero test to the execute stage	2017-12-30 14:12:23 +00:00
rv32_control.sv	Move CSR access to the execute stage	2017-12-30 11:34:14 +00:00
rv32_csrs.sv	Disable CSR writes if the execute stage is stalled	2018-01-01 19:30:31 +00:00
rv32_decode.sv	Add missing csr_src connection from the control unit to the flip flop	2017-12-30 15:37:01 +00:00
rv32_execute.sv	Disable CSR writes if the execute stage is stalled	2018-01-01 19:30:31 +00:00
rv32_fetch.sv	Add static branch prediction	2017-12-30 13:48:14 +00:00
rv32_hazard.sv	Add static branch prediction	2017-12-30 13:48:14 +00:00
rv32_imm.sv	Split decode stage into smaller modules	2017-12-27 14:05:09 +00:00
rv32_mem.sv	Move result zero/non-zero test to the execute stage	2017-12-30 14:12:23 +00:00
rv32_opcodes.sv	Add static branch prediction	2017-12-30 13:48:14 +00:00
rv32_regs.sv	Explicitly instantiate all registers to 0	2017-12-31 15:38:07 +00:00
start.s	Replace x0 with zero	2018-01-05 20:42:57 +00:00
sync.sv	Fix compatibility with iverilog	2017-12-09 21:03:45 +00:00
top.sv	support up5k FPGA with internal OSC	2018-01-23 18:17:44 +01:00
top.tcl	add TCL script for firmware creation	2018-01-23 19:47:00 +01:00
uart.sv	Merge memory bus inputs/outputs in the port list	2017-12-12 21:15:11 +00:00

README.md

Icicle

Introduction

Icicle is a 32-bit RISC-V system on chip for iCE40 HX8K FPGAs. It can be built with the open-source Project IceStorm toolchain and currently targets the iCE40-HX8K breakout board.

Current features

RV32I core with a classic 5-stage RISC pipeline, static branch prediction, bypassing and interlocking. It currently implements the entire user ISA (except ECALL and EBREAK) and parts of the privileged ISA.
Shared instruction and data memory (8 KiB, implemented with FPGA block RAM).
Memory-mapped UART and LEDs.

Dependencies

Building and testing

Run make syntax to check the syntax with Icarus, which has a stricter parser than Yosys.
Run make to synthesize the design, place and route, compile the demo program in progmem.c and create the bitstream.
Connect the iCE40-HX8K breakout board and configure the jumpers for direct SRAM programming.
Run make flash to program the bitstream. icetime is used to check that the design meets timing closure. The target fails if it does not.
4 of the 8 LEDs should turn on (with an on, off, on, off pattern). Run picocom /dev/ttyUSBN (replacing ttyUSBN with the name of the serial port) to connect to the serial port. Hello, world! should be printed once per second.

The make stat target runs icebox_stat and the make time target prints the icetime report.

The Makefile runs the IceStorm toolchain in quiet mode. Unset the QUIET variable to run the toolchain in verbose mode - e.g. make QUIET=.

Planned features

Use remaining block RAM tiles to eke out as much memory as possible.
Implement remaining bits of the user ISA.
Implement machine mode from the privileged ISA.
Interrupts/exceptions.
Unaligned memory access support.
Memory-mapped GPIOs.
Memory-mapped XIP/SPI flash.
Improved reset support (a reset signal + boot ROM to zero all the registers).
Automated tests.
Multiply/divide support.
Compressed instruction support.

Size and performance

The entire system on chip currently occupies around 2,000 LUTs on an iCE40 when synthesized with Yosys.

It's currently clocked at 24 MHz but icetime estimates it could be clocked at ~30-35 MHz (depending on how lucky arachne-pnr is).

The core is capable of issuing and retiring one instruction per clock cycle, although the actual number of instructions per cycle will be slightly less than this in practice due to interlocking, branch mispredictions and the shared memory bus.

License

This project is available under the terms of the ISC license, which is similar to the 2-clause BSD license. See the LICENSE file for the copyright information and licensing terms.