85 lines
2.2 KiB
Systemverilog
85 lines
2.2 KiB
Systemverilog
`ifndef RV32_FETCH
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`define RV32_FETCH
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`include "rv32_opcodes.sv"
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module rv32_fetch (
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input clk,
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/* control in (from hazard) */
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input stall_in,
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input flush_in,
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/* control in (from mem) */
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input branch_mispredicted_in,
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/* data in (from mem) */
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input [31:0] branch_pc_in,
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/* data in (from memory bus) */
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input [31:0] instr_read_value_in,
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/* control out (to memory bus) */
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output logic instr_read_out,
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/* control out */
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output logic branch_predicted_taken_out,
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/* data out */
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output logic [31:0] pc_out,
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output logic [31:0] instr_out,
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/* data out (to memory bus) */
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output logic [31:0] instr_address_out
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);
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logic [31:0] next_pc;
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logic [31:0] pc;
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logic sign;
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logic [31:0] imm_j;
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logic [31:0] imm_b;
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logic [7:0] opcode;
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logic branch_predicted_taken;
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logic [31:0] branch_offset;
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assign pc = branch_mispredicted_in ? branch_pc_in : next_pc;
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assign instr_read_out = 1;
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assign instr_address_out = pc;
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assign sign = instr_read_value_in[31];
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assign imm_j = {{12{sign}}, instr_read_value_in[19:12], instr_read_value_in[20], instr_read_value_in[30:25], instr_read_value_in[24:21], 1'b0};
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assign imm_b = {{20{sign}}, instr_read_value_in[7], instr_read_value_in[30:25], instr_read_value_in[11:8], 1'b0};
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assign opcode = instr_read_value_in[7:0];
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always_comb begin
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case ({opcode, sign})
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{`RV32_OPCODE_JAL, 1'bx}: begin
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branch_predicted_taken = 1;
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branch_offset = imm_j;
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end
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{`RV32_OPCODE_BRANCH, 1'b1}: begin
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branch_predicted_taken = 1;
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branch_offset = imm_b;
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end
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default: begin
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branch_predicted_taken = 0;
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branch_offset = 32'd4;
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end
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endcase
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end
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always_ff @(posedge clk) begin
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if (!stall_in) begin
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branch_predicted_taken_out <= branch_predicted_taken;
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instr_out <= instr_read_value_in;
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next_pc <= pc + branch_offset;
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pc_out <= pc;
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if (flush_in)
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instr_out <= `RV32_INSTR_NOP;
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end
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end
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endmodule
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`endif
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