Graham Edgecombe
6c964c75e5
Add static branch prediction
2017-12-30 13:48:14 +00:00
Graham Edgecombe
9b1e27cc0d
Combine the instruction and data buses
2017-12-25 23:33:53 +00:00
Graham Edgecombe
22bce1bdeb
Fix compatibility with iverilog
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This commit:
* changes the type of all output variables to logic
* splits variable declaration and assignment
* declares variables before modules that use the variables
2017-12-09 21:03:45 +00:00
Graham Edgecombe
e801556428
Replace localparams at the root level with defines
...
iverilog doesn't support localparams at the root level.
2017-12-09 10:44:39 +00:00
Graham Edgecombe
86022d42a5
Follow the standard naming/commenting conventions in hazard-related code
2017-12-07 22:37:58 +00:00
Graham Edgecombe
eff39ad19b
Add flush and stall inputs to every stage
2017-12-07 22:37:58 +00:00
Graham Edgecombe
83b7d1c9b7
Add 'from stage' comments if inputs are not from the previous stage
2017-12-07 22:37:58 +00:00
Graham Edgecombe
eb053503f7
Populate instr_mem with a test assembly program
2017-12-02 18:07:37 +00:00
Graham Edgecombe
86f6e0eec1
Add branching support
2017-12-02 15:23:12 +00:00
Graham Edgecombe
efb33456f9
Add include guards
2017-12-01 23:30:33 +00:00
Graham Edgecombe
ed238e5e9b
Use -noautowire to avoid using logic in every input/output declaration
2017-12-01 18:49:48 +00:00
Graham Edgecombe
4a4dee334d
Add initial fetch/decode stages
2017-12-01 08:46:43 +00:00
