Use -noautowire to avoid using logic in every input/output declaration

rv32.sv

@@ -2,7 +2,7 @@
 `include "rv32_fetch.sv"
 
 module rv32 (
-    input logic clk
+    input clk
 );
     rv32_fetch fetch (
         .clk(clk),

rv32_decode.sv

@@ -2,20 +2,20 @@
 `include "rv32_regs.sv"
 
 module rv32_decode (
-    input logic clk,
+    input clk,
 
     /* data in */
-    input logic [31:0] pc_in,
-    input logic [31:0] instr_in,
+    input [31:0] pc_in,
+    input [31:0] instr_in,
 
     /* control out */
-    output logic valid,
+    output valid,
 
     /* data out */
-    output logic [31:0] pc_out,
-    output logic [31:0] rs1_value_out,
-    output logic [31:0] rs2_value_out,
-    output logic [31:0] imm_out
+    output [31:0] pc_out,
+    output [31:0] rs1_value_out,
+    output [31:0] rs2_value_out,
+    output [31:0] imm_out
 );
     logic [6:0] funct7 = instr_in[31:25];
     logic [4:0] rs2    = instr_in[24:20];

rv32_fetch.sv

@@ -1,9 +1,9 @@
 module rv32_fetch (
-    input logic clk,
+    input clk,
 
     /* data out */
-    output logic [31:0] pc_out,
-    output logic [31:0] instr_out
+    output [31:0] pc_out,
+    output [31:0] instr_out
 );
     logic [31:0] instr_mem [255:0];
     logic [31:0] pc;

rv32_regs.sv

@@ -1,18 +1,18 @@
 module rv32_regs (
-    input logic clk,
+    input clk,
 
     /* control in */
-    input logic [4:0] rs1_in,
-    input logic [4:0] rs2_in,
-    input logic [4:0] rd_in,
-    input logic rd_writeback_in,
+    input [4:0] rs1_in,
+    input [4:0] rs2_in,
+    input [4:0] rd_in,
+    input rd_writeback_in,
 
     /* data in */
-    input logic [31:0] rd_value_in,
+    input [31:0] rd_value_in,
 
     /* data out */
-    output logic [31:0] rs1_value_out,
-    output logic [31:0] rs2_value_out
+    output [31:0] rs1_value_out,
+    output [31:0] rs2_value_out
 );
     logic [31:0] regs [31:0];
 

top.ys

@@ -1,4 +1,4 @@
-read_verilog -sv top.sv
+read_verilog -noautowire -sv top.sv
 proc
 opt
 alumacc