25 lines
423 B
Systemverilog
25 lines
423 B
Systemverilog
`include "rv32_decode.sv"
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`include "rv32_fetch.sv"
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module rv32 (
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input clk
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);
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rv32_fetch fetch (
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.clk(clk),
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/* data out */
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.pc_out(fetch_pc),
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.instr_out(fetch_instr)
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);
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logic [31:0] fetch_pc;
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logic [31:0] fetch_instr;
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rv32_decode decode (
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.clk(clk),
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/* data in */
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.pc_in(fetch_pc),
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.instr_in(fetch_instr)
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);
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endmodule
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