pingu_98/icicle
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  • 5c3487be49 add PCF file for UP5K part on upduino master Andrea Venturi 2018-01-23 19:47:28 +0100
  • e93fb454bf add TCL script for firmware creation Andrea Venturi 2018-01-23 19:47:00 +0100
  • a9c0d91341 support up5k FPGA with internal OSC Andrea Venturi 2018-01-23 18:17:44 +0100
  • f5a046f678 Replace x0 with zero Graham Edgecombe 2018-01-05 20:42:57 +0000
  • a1fb770982 Add README and LICENSE Graham Edgecombe 2018-01-04 22:04:40 +0000
  • b4c58919b6 Disable CSR writes if the execute stage is stalled Graham Edgecombe 2018-01-01 19:30:31 +0000
  • d7e417df0b Add BAUD_RATE constant Graham Edgecombe 2018-01-01 14:39:05 +0000
  • 2a1ec25a66 Make RV32_ISA_VALUE comment consistent with the opcodes comment Graham Edgecombe 2017-12-31 17:11:56 +0000
  • e9d60ba3e9 Hard-wire pmpcfg and pmpaddr CSRs to 0 Graham Edgecombe 2017-12-31 16:55:11 +0000
  • 0f094c67db Hard-wire hpmevent and hpmcounter CSRs to 0 Graham Edgecombe 2017-12-31 16:03:11 +0000
  • 5011731355 Add mcycle and minstret CSRs Graham Edgecombe 2017-12-31 15:43:06 +0000
  • 98811cce86 Explicitly instantiate all registers to 0 Graham Edgecombe 2017-12-31 15:38:07 +0000
  • 26ec3542e4 Add mscratch CSR Graham Edgecombe 2017-12-31 11:13:07 +0000
  • 73717d320d Fix CSR write value mux Graham Edgecombe 2017-12-31 11:12:56 +0000
  • 63c5585fda Add misa CSR Graham Edgecombe 2017-12-31 10:36:25 +0000
  • a430c50f16 Add machine information CSRs Graham Edgecombe 2017-12-31 10:29:17 +0000
  • 426daa39d6 Replace binary CSR constants with hex Graham Edgecombe 2017-12-31 10:15:46 +0000
  • 62ea036b23 Add missing csr_src connection from the control unit to the flip flop Graham Edgecombe 2017-12-30 15:37:01 +0000
  • dd52e5c318 Declare {ram,leds,uart}_sel before using them Graham Edgecombe 2017-12-30 15:24:52 +0000
  • 8024a6075f Move result zero/non-zero test to the execute stage Graham Edgecombe 2017-12-30 14:12:23 +0000
  • 6c964c75e5 Add static branch prediction Graham Edgecombe 2017-12-30 13:48:14 +0000
  • 276688f9ef Move CSR access to the execute stage Graham Edgecombe 2017-12-30 11:34:14 +0000
  • b0c05a908e Move mem_read_value declaration below the memory access unit comment Graham Edgecombe 2017-12-30 11:02:18 +0000
  • eac6a20040 Only stall the pipeline if rs1/rs2 are read Graham Edgecombe 2017-12-29 20:37:02 +0000
  • 3f19fc4226 Replace parallel 32-bit adders with a single 64-bit adder Graham Edgecombe 2017-12-29 17:24:04 +0000
  • 3806106b1c Replace -Os with -O2 Graham Edgecombe 2017-12-29 17:18:36 +0000
  • d73b443ecc Replace __asm__ with asm Graham Edgecombe 2017-12-29 17:09:53 +0000
  • 08e79c32e0 Delete timing/icestat reports in the clean target Graham Edgecombe 2017-12-29 16:27:35 +0000
  • 21e7ee2b8c Remove unused stall_in input from rv32_csrs Graham Edgecombe 2017-12-29 16:26:11 +0000
  • 63cd024d5c Fix instret rollover Graham Edgecombe 2017-12-29 16:23:33 +0000
  • 0939363a3f Add rdcycle demo Graham Edgecombe 2017-12-29 16:09:41 +0000
  • 20de15c3e5 Pass -Os to gcc Graham Edgecombe 2017-12-29 16:09:19 +0000
  • 0bc2871ded Link with gcc instead of ld Graham Edgecombe 2017-12-29 15:48:16 +0000
  • 4b6218c2a8 Add initial CSR support Graham Edgecombe 2017-12-29 15:29:15 +0000
  • de1f936cdd Implement FENCE.I Graham Edgecombe 2017-12-27 15:23:59 +0000
  • 0013935bb0 Split decode stage into smaller modules Graham Edgecombe 2017-12-27 14:05:09 +0000
  • 2b1e0de9de Propagate mem_fence signal through the pipeline Graham Edgecombe 2017-12-26 16:46:01 +0000
  • f8b8842abc Bump FREQ_PLL to 36 MHz again Graham Edgecombe 2017-12-26 14:40:54 +0000
  • b73a0155dd Swap byte order in the ram module Graham Edgecombe 2017-12-26 14:15:12 +0000
  • 3c2f7518ec Add new 'hello world' demo program Graham Edgecombe 2017-12-26 13:46:20 +0000
  • 2ba26fc7e6 Switch from big- to little-endian ordering in the memory access stage Graham Edgecombe 2017-12-26 13:38:07 +0000
  • b578251132 Add rodata to the linker script Graham Edgecombe 2017-12-25 23:42:32 +0000
  • 9b1e27cc0d Combine the instruction and data buses Graham Edgecombe 2017-12-25 23:12:55 +0000
  • 7f81e495b3 Add write enable output to the memory bus Graham Edgecombe 2017-12-17 20:47:17 +0000
  • 7ef3e831ce Prefix data bus wire names with data_ Graham Edgecombe 2017-12-17 19:57:00 +0000
  • b01e81357d Re-use the main adder to implement the LUI, JAL and JALR instructions Graham Edgecombe 2017-12-16 12:42:11 +0000
  • 135a081fd4 Remove unused clk_div.sv include Graham Edgecombe 2017-12-16 11:32:32 +0000
  • bfbe3be490 Add FREQ macro to avoid hard-coding 36 MHz Graham Edgecombe 2017-12-15 20:21:12 +0000
  • e4e2e65293 Port example program to C Graham Edgecombe 2017-12-15 20:08:55 +0000
  • d97f8c5e8e Add yosys-config --datdir workaround Graham Edgecombe 2017-12-15 18:35:26 +0000
  • 9f8ca8c496 Add GitLab CI config Graham Edgecombe 2017-12-15 18:31:48 +0000
  • a713290deb Add MRET and WFI to the decoder Graham Edgecombe 2017-12-14 23:53:49 +0000
  • c61234f7e4 Order ECALL/EBREAK consistently Graham Edgecombe 2017-12-14 23:52:53 +0000
  • d5c87dacf6 Add MRET and WFI instruction encoding Graham Edgecombe 2017-12-14 23:46:18 +0000
  • 5f84ff150b Simplify giant case statement in the decoder Graham Edgecombe 2017-12-12 22:37:25 +0000
  • d6f5bb2218 Add initial support for SYSTEM instructions to the decoder Graham Edgecombe 2017-12-12 21:53:59 +0000
  • 9259065656 Rename check target to syntax Graham Edgecombe 2017-12-12 21:20:49 +0000
  • 04dc25c5dc Merge memory bus inputs/outputs in the port list Graham Edgecombe 2017-12-12 21:15:11 +0000
  • f571ab29eb Rename rv32_branch to rv32_branch_unit Graham Edgecombe 2017-12-12 21:05:02 +0000
  • 58ff5c9ec7 Rename rv32_hazard to rv32_hazard_unit Graham Edgecombe 2017-12-12 21:04:33 +0000
  • f19d41c8a2 Replace $(TOP).bin with $(BIN) Graham Edgecombe 2017-12-10 14:10:51 +0000
  • b8e848cb0e Add SV variable to replace $(TOP).sv Graham Edgecombe 2017-12-10 14:10:33 +0000
  • 8e1f64eea0 Add progmem_syn.hex dependency to the check target Graham Edgecombe 2017-12-10 09:25:37 +0000
  • 9c8dfd1b82 Replace top.sv with $(TOP).sv Graham Edgecombe 2017-12-10 09:25:18 +0000
  • 0306c4dc72 Add iverilog syntax check target Graham Edgecombe 2017-12-09 21:33:51 +0000
  • 22bce1bdeb Fix compatibility with iverilog Graham Edgecombe 2017-12-09 21:03:45 +0000
  • de54271076 Fix width of RV32_BRANCH_OP constants Graham Edgecombe 2017-12-09 10:46:08 +0000
  • e801556428 Replace localparams at the root level with defines Graham Edgecombe 2017-12-09 10:44:39 +0000
  • bf7b1bef4f Pass -full to opt Graham Edgecombe 2017-12-08 22:29:22 +0000
  • 02a742b3c9 Remove trailing comma in SB_IO declaration Graham Edgecombe 2017-12-07 22:49:28 +0000
  • 9f036f6630 Add UART demo program Graham Edgecombe 2017-12-07 22:12:50 +0000
  • 66089359fe Make the meaning of the TX write ready status bit clearer Graham Edgecombe 2017-12-07 21:32:25 +0000
  • 02909b1f98 Add receive support to the UART Graham Edgecombe 2017-12-07 21:29:58 +0000
  • 4d9d405c05 Fix TX ready output Graham Edgecombe 2017-12-07 20:22:11 +0000
  • 6d638404f1 Add new memory-mapped UART Graham Edgecombe 2017-12-06 22:29:18 +0000
  • bb5f2c8d8c Fix ram_sel/leds_sel decoding Graham Edgecombe 2017-12-06 22:10:30 +0000
  • 82394bce1c Add read_out signal to the memory bus Graham Edgecombe 2017-12-06 15:36:46 +0000
  • 460159a392 Rename rd_writeback to rd_write Graham Edgecombe 2017-12-06 14:53:42 +0000
  • 36b7d33850 Read mem_{read,write}_en to mem_{read,write} Graham Edgecombe 2017-12-06 14:51:55 +0000
  • cddfd0587d Add loopback UART Graham Edgecombe 2017-12-06 14:45:08 +0000
  • 3d26eb67ed Synchronize the PLL locked output with the clock Graham Edgecombe 2017-12-06 08:41:38 +0000
  • 3ed53406a0 Move timing closure requirement to the flash target Graham Edgecombe 2017-12-06 08:38:01 +0000
  • b4e0e6ceb0 Store icebox_stat output in top.stat Graham Edgecombe 2017-12-06 08:36:51 +0000
  • 967f3d1414 Delete pll.sv in the clean target Graham Edgecombe 2017-12-06 08:33:09 +0000
  • 560f45d3ca Require timing closure to be met before creating the bitstream Graham Edgecombe 2017-12-06 08:32:30 +0000
  • 260c0429bd Store timing report in top.rpt Graham Edgecombe 2017-12-06 08:30:32 +0000
  • 26f6b88da8 Add PLL Graham Edgecombe 2017-12-06 08:26:00 +0000
  • a8225b8ebb Fix clock connected to the LEDs flip flop Graham Edgecombe 2017-12-06 08:24:15 +0000
  • 998dd0f0ba Add synchronizer module Graham Edgecombe 2017-12-06 08:22:30 +0000
  • 3be5990b17 Use t0 register in demo program Graham Edgecombe 2017-12-06 08:18:59 +0000
  • 365d3e37c6 Memory map the LEDs Graham Edgecombe 2017-12-06 08:14:42 +0000
  • 0be0da3917 Add memory address decoding Graham Edgecombe 2017-12-06 08:01:51 +0000
  • cc1f73e19e Replace pointless if with assign in the hazard unit Graham Edgecombe 2017-12-06 06:49:26 +0000
  • bf6622d9f4 Add Egyptian multiplication demo program Graham Edgecombe 2017-12-05 23:12:33 +0000
  • 281009a64c Increase size of data RAM to 8 KB Graham Edgecombe 2017-12-05 22:45:39 +0000
  • 018faac560 Add memory bus and move data memory to a separate module Graham Edgecombe 2017-12-05 22:00:47 +0000
  • 03ecd3a97d Remove unused mem_read_en output Graham Edgecombe 2017-12-05 21:14:16 +0000
  • da26f86f25 Remove two cycle load-use stall Graham Edgecombe 2017-12-05 21:12:37 +0000
  • 9541f198c2 Revert "Reset {rs1,rs2_out} when flushing the decode stage" Graham Edgecombe 2017-12-05 21:08:32 +0000
  • e7ae22bf31 Remove _ops.sv files Graham Edgecombe 2017-12-05 19:54:01 +0000