This commit is contained in:
Graham Edgecombe 2017-12-06 08:26:00 +00:00
parent a8225b8ebb
commit 26f6b88da8
3 changed files with 18 additions and 11 deletions

1
.gitignore vendored
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@ -5,5 +5,6 @@
*.blif
*.hex
*.o
/pll.sv
!.git*
!.mailmap

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@ -1,5 +1,6 @@
QUIET = -q
SRC = $(wildcard *.sv)
PLL = pll.sv
SRC = $(sort $(wildcard *.sv) $(PLL))
TOP = top
YS = $(TOP).ys
BLIF = $(TOP).blif
@ -11,6 +12,7 @@ DEVICE = 8k
PACKAGE = ct256
PCF = ice40hx8k-b-evn.pcf
FREQ_OSC = 12
FREQ_PLL = 36
TARGET = riscv64-unknown-elf
AS = $(TARGET)-as
ASFLAGS = -march=rv32i -mabi=ilp32
@ -31,6 +33,9 @@ progmem.hex: progmem.o
progmem_syn.hex:
icebram -g 32 256 > $@
$(PLL):
icepll $(QUIET) -i $(FREQ_OSC) -o $(FREQ_PLL) -m -f $@
$(BLIF): $(YS) $(SRC) progmem_syn.hex
yosys $(QUIET) -s $<
@ -44,7 +49,7 @@ $(BIN): $(ASC)
icepack $< $@
time: $(ASC_SYN) $(PCF)
icetime -t -m -d $(SPEED)$(DEVICE) -P $(PACKAGE) -p $(PCF) -c $(FREQ_OSC) $<
icetime -t -m -d $(SPEED)$(DEVICE) -P $(PACKAGE) -p $(PCF) -c $(FREQ_PLL) $<
stat: $(ASC_SYN)
icebox_stat $<

19
top.sv
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@ -1,4 +1,5 @@
`include "clk_div.sv"
`include "pll.sv"
`include "ram.sv"
`include "rv32.sv"
@ -35,17 +36,17 @@ module top (
.D_OUT_0({flash_io1_out, flash_io0_out})
);
logic clk_slow;
logic pll_clk;
logic pll_locked;
clk_div #(
.LOG_DIVISOR(18)
) clk_div (
.clk_in(clk),
.clk_out(clk_slow)
pll pll (
.clock_in(clk),
.clock_out(pll_clk),
.locked(pll_locked)
);
rv32 rv32 (
.clk(clk_slow),
.clk(pll_clk),
/* control out */
.write_mask_out(mem_write_mask),
@ -70,7 +71,7 @@ module top (
logic [31:0] ram_read_value;
ram ram (
.clk(clk_slow),
.clk(pll_clk),
/* control in */
.sel_in(ram_sel),
@ -87,7 +88,7 @@ module top (
logic leds_sel = mem_address[31:0] == 32'b00000000_00000001_00000000_000000??;
logic [31:0] leds_read_value = {24'b0, leds_sel ? leds : 8'b0};
always_ff @(posedge clk_slow) begin
always_ff @(posedge pll_clk) begin
if (leds_sel && mem_write_mask[0])
leds <= mem_write_value[7:0];
end