Add PLL
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parent
a8225b8ebb
commit
26f6b88da8
3 changed files with 18 additions and 11 deletions
1
.gitignore
vendored
1
.gitignore
vendored
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@ -5,5 +5,6 @@
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*.blif
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*.hex
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*.o
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/pll.sv
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!.git*
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!.mailmap
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9
Makefile
9
Makefile
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@ -1,5 +1,6 @@
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QUIET = -q
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SRC = $(wildcard *.sv)
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PLL = pll.sv
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SRC = $(sort $(wildcard *.sv) $(PLL))
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TOP = top
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YS = $(TOP).ys
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BLIF = $(TOP).blif
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@ -11,6 +12,7 @@ DEVICE = 8k
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PACKAGE = ct256
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PCF = ice40hx8k-b-evn.pcf
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FREQ_OSC = 12
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FREQ_PLL = 36
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TARGET = riscv64-unknown-elf
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AS = $(TARGET)-as
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ASFLAGS = -march=rv32i -mabi=ilp32
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@ -31,6 +33,9 @@ progmem.hex: progmem.o
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progmem_syn.hex:
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icebram -g 32 256 > $@
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$(PLL):
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icepll $(QUIET) -i $(FREQ_OSC) -o $(FREQ_PLL) -m -f $@
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$(BLIF): $(YS) $(SRC) progmem_syn.hex
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yosys $(QUIET) -s $<
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@ -44,7 +49,7 @@ $(BIN): $(ASC)
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icepack $< $@
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time: $(ASC_SYN) $(PCF)
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icetime -t -m -d $(SPEED)$(DEVICE) -P $(PACKAGE) -p $(PCF) -c $(FREQ_OSC) $<
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icetime -t -m -d $(SPEED)$(DEVICE) -P $(PACKAGE) -p $(PCF) -c $(FREQ_PLL) $<
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stat: $(ASC_SYN)
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icebox_stat $<
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19
top.sv
19
top.sv
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@ -1,4 +1,5 @@
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`include "clk_div.sv"
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`include "pll.sv"
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`include "ram.sv"
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`include "rv32.sv"
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@ -35,17 +36,17 @@ module top (
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.D_OUT_0({flash_io1_out, flash_io0_out})
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);
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logic clk_slow;
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logic pll_clk;
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logic pll_locked;
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clk_div #(
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.LOG_DIVISOR(18)
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) clk_div (
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.clk_in(clk),
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.clk_out(clk_slow)
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pll pll (
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.clock_in(clk),
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.clock_out(pll_clk),
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.locked(pll_locked)
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);
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rv32 rv32 (
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.clk(clk_slow),
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.clk(pll_clk),
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/* control out */
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.write_mask_out(mem_write_mask),
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@ -70,7 +71,7 @@ module top (
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logic [31:0] ram_read_value;
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ram ram (
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.clk(clk_slow),
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.clk(pll_clk),
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/* control in */
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.sel_in(ram_sel),
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@ -87,7 +88,7 @@ module top (
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logic leds_sel = mem_address[31:0] == 32'b00000000_00000001_00000000_000000??;
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logic [31:0] leds_read_value = {24'b0, leds_sel ? leds : 8'b0};
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always_ff @(posedge clk_slow) begin
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always_ff @(posedge pll_clk) begin
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if (leds_sel && mem_write_mask[0])
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leds <= mem_write_value[7:0];
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end
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