Hard-wire hpmevent and hpmcounter CSRs to 0
This commit is contained in:
Graham Edgecombe
parent
5011731355
commit
0f094c67db
1 changed files with 207 additions and 33 deletions
240
rv32_csrs.sv
240
rv32_csrs.sv
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@ -1,22 +1,109 @@
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`ifndef RV32_CSRS
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`define RV32_CSRS
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`define RV32_CSR_MISA 12'h301
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`define RV32_CSR_MSCRATCH 12'h340
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`define RV32_CSR_MCYCLE 12'hB00
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`define RV32_CSR_MINSTRET 12'hB02
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`define RV32_CSR_MCYCLEH 12'hB80
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`define RV32_CSR_MINSTRETH 12'hB82
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`define RV32_CSR_CYCLE 12'hC00
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`define RV32_CSR_TIME 12'hC01
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`define RV32_CSR_INSTRET 12'hC02
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`define RV32_CSR_CYCLEH 12'hC80
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`define RV32_CSR_TIMEH 12'hC81
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`define RV32_CSR_INSTRETH 12'hC82
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`define RV32_CSR_MVENDORID 12'hF11
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`define RV32_CSR_MARCHID 12'hF12
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`define RV32_CSR_MIMPID 12'hF13
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`define RV32_CSR_MHARTID 12'hF14
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`define RV32_CSR_MISA 12'h301
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`define RV32_CSR_MHPMEVENT3 12'h323
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`define RV32_CSR_MHPMEVENT4 12'h324
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`define RV32_CSR_MHPMEVENT5 12'h325
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`define RV32_CSR_MHPMEVENT6 12'h326
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`define RV32_CSR_MHPMEVENT7 12'h327
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`define RV32_CSR_MHPMEVENT8 12'h328
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`define RV32_CSR_MHPMEVENT9 12'h329
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`define RV32_CSR_MHPMEVENT10 12'h32A
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`define RV32_CSR_MHPMEVENT11 12'h32B
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`define RV32_CSR_MHPMEVENT12 12'h32C
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`define RV32_CSR_MHPMEVENT13 12'h32D
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`define RV32_CSR_MHPMEVENT14 12'h32E
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`define RV32_CSR_MHPMEVENT15 12'h32F
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`define RV32_CSR_MHPMEVENT16 12'h330
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`define RV32_CSR_MHPMEVENT17 12'h331
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`define RV32_CSR_MHPMEVENT18 12'h332
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`define RV32_CSR_MHPMEVENT19 12'h333
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`define RV32_CSR_MHPMEVENT20 12'h334
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`define RV32_CSR_MHPMEVENT21 12'h335
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`define RV32_CSR_MHPMEVENT22 12'h336
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`define RV32_CSR_MHPMEVENT23 12'h337
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`define RV32_CSR_MHPMEVENT24 12'h338
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`define RV32_CSR_MHPMEVENT25 12'h339
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`define RV32_CSR_MHPMEVENT26 12'h33A
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`define RV32_CSR_MHPMEVENT27 12'h33B
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`define RV32_CSR_MHPMEVENT28 12'h33C
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`define RV32_CSR_MHPMEVENT29 12'h33D
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`define RV32_CSR_MHPMEVENT30 12'h33E
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`define RV32_CSR_MHPMEVENT31 12'h33F
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`define RV32_CSR_MSCRATCH 12'h340
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`define RV32_CSR_MCYCLE 12'hB00
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`define RV32_CSR_MINSTRET 12'hB02
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`define RV32_CSR_MHPMCOUNTER3 12'hB03
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`define RV32_CSR_MHPMCOUNTER4 12'hB04
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`define RV32_CSR_MHPMCOUNTER5 12'hB05
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`define RV32_CSR_MHPMCOUNTER6 12'hB06
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`define RV32_CSR_MHPMCOUNTER7 12'hB07
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`define RV32_CSR_MHPMCOUNTER8 12'hB08
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`define RV32_CSR_MHPMCOUNTER9 12'hB09
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`define RV32_CSR_MHPMCOUNTER10 12'hB0A
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`define RV32_CSR_MHPMCOUNTER11 12'hB0B
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`define RV32_CSR_MHPMCOUNTER12 12'hB0C
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`define RV32_CSR_MHPMCOUNTER13 12'hB0D
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`define RV32_CSR_MHPMCOUNTER14 12'hB0E
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`define RV32_CSR_MHPMCOUNTER15 12'hB0F
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`define RV32_CSR_MHPMCOUNTER16 12'hB10
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`define RV32_CSR_MHPMCOUNTER17 12'hB11
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`define RV32_CSR_MHPMCOUNTER18 12'hB12
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`define RV32_CSR_MHPMCOUNTER19 12'hB13
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`define RV32_CSR_MHPMCOUNTER20 12'hB14
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`define RV32_CSR_MHPMCOUNTER21 12'hB15
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`define RV32_CSR_MHPMCOUNTER22 12'hB16
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`define RV32_CSR_MHPMCOUNTER23 12'hB17
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`define RV32_CSR_MHPMCOUNTER24 12'hB18
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`define RV32_CSR_MHPMCOUNTER25 12'hB19
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`define RV32_CSR_MHPMCOUNTER26 12'hB1A
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`define RV32_CSR_MHPMCOUNTER27 12'hB1B
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`define RV32_CSR_MHPMCOUNTER28 12'hB1C
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`define RV32_CSR_MHPMCOUNTER29 12'hB1D
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`define RV32_CSR_MHPMCOUNTER30 12'hB1E
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`define RV32_CSR_MHPMCOUNTER31 12'hB1F
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`define RV32_CSR_MCYCLEH 12'hB80
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`define RV32_CSR_MINSTRETH 12'hB82
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`define RV32_CSR_MHPMCOUNTER3H 12'hB83
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`define RV32_CSR_MHPMCOUNTER4H 12'hB84
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`define RV32_CSR_MHPMCOUNTER5H 12'hB85
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`define RV32_CSR_MHPMCOUNTER6H 12'hB86
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`define RV32_CSR_MHPMCOUNTER7H 12'hB87
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`define RV32_CSR_MHPMCOUNTER8H 12'hB88
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`define RV32_CSR_MHPMCOUNTER9H 12'hB89
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`define RV32_CSR_MHPMCOUNTER10H 12'hB8A
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`define RV32_CSR_MHPMCOUNTER11H 12'hB8B
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`define RV32_CSR_MHPMCOUNTER12H 12'hB8C
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`define RV32_CSR_MHPMCOUNTER13H 12'hB8D
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`define RV32_CSR_MHPMCOUNTER14H 12'hB8E
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`define RV32_CSR_MHPMCOUNTER15H 12'hB8F
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`define RV32_CSR_MHPMCOUNTER16H 12'hB90
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`define RV32_CSR_MHPMCOUNTER17H 12'hB91
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`define RV32_CSR_MHPMCOUNTER18H 12'hB92
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`define RV32_CSR_MHPMCOUNTER19H 12'hB93
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`define RV32_CSR_MHPMCOUNTER20H 12'hB94
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`define RV32_CSR_MHPMCOUNTER21H 12'hB95
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`define RV32_CSR_MHPMCOUNTER22H 12'hB96
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`define RV32_CSR_MHPMCOUNTER23H 12'hB97
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`define RV32_CSR_MHPMCOUNTER24H 12'hB98
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`define RV32_CSR_MHPMCOUNTER25H 12'hB99
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`define RV32_CSR_MHPMCOUNTER26H 12'hB9A
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`define RV32_CSR_MHPMCOUNTER27H 12'hB9B
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`define RV32_CSR_MHPMCOUNTER28H 12'hB9C
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`define RV32_CSR_MHPMCOUNTER29H 12'hB9D
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`define RV32_CSR_MHPMCOUNTER30H 12'hB9E
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`define RV32_CSR_MHPMCOUNTER31H 12'hB9F
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`define RV32_CSR_CYCLE 12'hC00
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`define RV32_CSR_TIME 12'hC01
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`define RV32_CSR_INSTRET 12'hC02
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`define RV32_CSR_CYCLEH 12'hC80
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`define RV32_CSR_TIMEH 12'hC81
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`define RV32_CSR_INSTRETH 12'hC82
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`define RV32_CSR_MVENDORID 12'hF11
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`define RV32_CSR_MARCHID 12'hF12
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`define RV32_CSR_MIMPID 12'hF13
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`define RV32_CSR_MHARTID 12'hF14
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`define RV32_CSR_WRITE_OP_RW 2'b00
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`define RV32_CSR_WRITE_OP_RS 2'b01
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@ -59,23 +146,110 @@ module rv32_csrs (
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always_comb begin
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case (csr_in)
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`RV32_CSR_MISA: read_value_out = `RV32_MISA_VALUE;
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`RV32_CSR_MSCRATCH: read_value_out = mscratch;
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`RV32_CSR_MCYCLE: read_value_out = cycle[31:0];
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`RV32_CSR_MINSTRET: read_value_out = instret[31:0];
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`RV32_CSR_MCYCLEH: read_value_out = cycle[63:32];
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`RV32_CSR_MINSTRETH: read_value_out = instret[63:32];
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`RV32_CSR_CYCLE: read_value_out = cycle[31:0];
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`RV32_CSR_TIME: read_value_out = cycle[31:0];
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`RV32_CSR_INSTRET: read_value_out = instret[31:0];
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`RV32_CSR_CYCLEH: read_value_out = cycle[63:32];
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`RV32_CSR_TIMEH: read_value_out = cycle[63:32];
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`RV32_CSR_INSTRETH: read_value_out = instret[63:32];
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`RV32_CSR_MVENDORID: read_value_out = 32'b0;
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`RV32_CSR_MARCHID: read_value_out = 32'b0;
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`RV32_CSR_MIMPID: read_value_out = 32'b0;
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`RV32_CSR_MHARTID: read_value_out = 32'b0;
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default: read_value_out = 32'bx;
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`RV32_CSR_MISA: read_value_out = `RV32_MISA_VALUE;
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`RV32_CSR_MHPMEVENT3: read_value_out = 32'b0;
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`RV32_CSR_MHPMEVENT4: read_value_out = 32'b0;
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`RV32_CSR_MHPMEVENT5: read_value_out = 32'b0;
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`RV32_CSR_MHPMEVENT6: read_value_out = 32'b0;
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`RV32_CSR_MHPMEVENT7: read_value_out = 32'b0;
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`RV32_CSR_MHPMEVENT7: read_value_out = 32'b0;
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`RV32_CSR_MHPMEVENT9: read_value_out = 32'b0;
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`RV32_CSR_MHPMEVENT10: read_value_out = 32'b0;
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`RV32_CSR_MHPMEVENT11: read_value_out = 32'b0;
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`RV32_CSR_MHPMEVENT12: read_value_out = 32'b0;
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`RV32_CSR_MHPMEVENT13: read_value_out = 32'b0;
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`RV32_CSR_MHPMEVENT14: read_value_out = 32'b0;
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`RV32_CSR_MHPMEVENT15: read_value_out = 32'b0;
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`RV32_CSR_MHPMEVENT16: read_value_out = 32'b0;
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`RV32_CSR_MHPMEVENT17: read_value_out = 32'b0;
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`RV32_CSR_MHPMEVENT18: read_value_out = 32'b0;
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`RV32_CSR_MHPMEVENT19: read_value_out = 32'b0;
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`RV32_CSR_MHPMEVENT20: read_value_out = 32'b0;
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`RV32_CSR_MHPMEVENT21: read_value_out = 32'b0;
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`RV32_CSR_MHPMEVENT22: read_value_out = 32'b0;
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`RV32_CSR_MHPMEVENT23: read_value_out = 32'b0;
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`RV32_CSR_MHPMEVENT24: read_value_out = 32'b0;
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`RV32_CSR_MHPMEVENT25: read_value_out = 32'b0;
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`RV32_CSR_MHPMEVENT26: read_value_out = 32'b0;
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`RV32_CSR_MHPMEVENT27: read_value_out = 32'b0;
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`RV32_CSR_MHPMEVENT28: read_value_out = 32'b0;
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`RV32_CSR_MHPMEVENT29: read_value_out = 32'b0;
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`RV32_CSR_MHPMEVENT30: read_value_out = 32'b0;
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`RV32_CSR_MHPMEVENT31: read_value_out = 32'b0;
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`RV32_CSR_MSCRATCH: read_value_out = mscratch;
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`RV32_CSR_MCYCLE: read_value_out = cycle[31:0];
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`RV32_CSR_MINSTRET: read_value_out = instret[31:0];
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`RV32_CSR_MHPMCOUNTER3: read_value_out = 32'b0;
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`RV32_CSR_MHPMCOUNTER4: read_value_out = 32'b0;
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`RV32_CSR_MHPMCOUNTER5: read_value_out = 32'b0;
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`RV32_CSR_MHPMCOUNTER6: read_value_out = 32'b0;
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`RV32_CSR_MHPMCOUNTER7: read_value_out = 32'b0;
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`RV32_CSR_MHPMCOUNTER8: read_value_out = 32'b0;
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`RV32_CSR_MHPMCOUNTER9: read_value_out = 32'b0;
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`RV32_CSR_MHPMCOUNTER10: read_value_out = 32'b0;
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`RV32_CSR_MHPMCOUNTER11: read_value_out = 32'b0;
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`RV32_CSR_MHPMCOUNTER12: read_value_out = 32'b0;
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`RV32_CSR_MHPMCOUNTER13: read_value_out = 32'b0;
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`RV32_CSR_MHPMCOUNTER14: read_value_out = 32'b0;
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`RV32_CSR_MHPMCOUNTER15: read_value_out = 32'b0;
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`RV32_CSR_MHPMCOUNTER16: read_value_out = 32'b0;
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`RV32_CSR_MHPMCOUNTER17: read_value_out = 32'b0;
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`RV32_CSR_MHPMCOUNTER18: read_value_out = 32'b0;
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`RV32_CSR_MHPMCOUNTER19: read_value_out = 32'b0;
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`RV32_CSR_MHPMCOUNTER20: read_value_out = 32'b0;
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`RV32_CSR_MHPMCOUNTER21: read_value_out = 32'b0;
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`RV32_CSR_MHPMCOUNTER22: read_value_out = 32'b0;
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`RV32_CSR_MHPMCOUNTER23: read_value_out = 32'b0;
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`RV32_CSR_MHPMCOUNTER24: read_value_out = 32'b0;
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`RV32_CSR_MHPMCOUNTER25: read_value_out = 32'b0;
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`RV32_CSR_MHPMCOUNTER26: read_value_out = 32'b0;
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`RV32_CSR_MHPMCOUNTER27: read_value_out = 32'b0;
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`RV32_CSR_MHPMCOUNTER28: read_value_out = 32'b0;
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`RV32_CSR_MHPMCOUNTER29: read_value_out = 32'b0;
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`RV32_CSR_MHPMCOUNTER30: read_value_out = 32'b0;
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`RV32_CSR_MHPMCOUNTER31: read_value_out = 32'b0;
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`RV32_CSR_MCYCLEH: read_value_out = cycle[63:32];
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`RV32_CSR_MINSTRETH: read_value_out = instret[63:32];
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`RV32_CSR_MHPMCOUNTER3H: read_value_out = 32'b0;
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`RV32_CSR_MHPMCOUNTER4H: read_value_out = 32'b0;
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`RV32_CSR_MHPMCOUNTER5H: read_value_out = 32'b0;
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`RV32_CSR_MHPMCOUNTER6H: read_value_out = 32'b0;
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`RV32_CSR_MHPMCOUNTER7H: read_value_out = 32'b0;
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`RV32_CSR_MHPMCOUNTER8H: read_value_out = 32'b0;
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`RV32_CSR_MHPMCOUNTER9H: read_value_out = 32'b0;
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`RV32_CSR_MHPMCOUNTER10H: read_value_out = 32'b0;
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`RV32_CSR_MHPMCOUNTER11H: read_value_out = 32'b0;
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`RV32_CSR_MHPMCOUNTER12H: read_value_out = 32'b0;
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`RV32_CSR_MHPMCOUNTER13H: read_value_out = 32'b0;
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`RV32_CSR_MHPMCOUNTER14H: read_value_out = 32'b0;
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`RV32_CSR_MHPMCOUNTER15H: read_value_out = 32'b0;
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`RV32_CSR_MHPMCOUNTER16H: read_value_out = 32'b0;
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`RV32_CSR_MHPMCOUNTER17H: read_value_out = 32'b0;
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`RV32_CSR_MHPMCOUNTER18H: read_value_out = 32'b0;
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`RV32_CSR_MHPMCOUNTER19H: read_value_out = 32'b0;
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`RV32_CSR_MHPMCOUNTER20H: read_value_out = 32'b0;
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`RV32_CSR_MHPMCOUNTER21H: read_value_out = 32'b0;
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`RV32_CSR_MHPMCOUNTER22H: read_value_out = 32'b0;
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`RV32_CSR_MHPMCOUNTER23H: read_value_out = 32'b0;
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`RV32_CSR_MHPMCOUNTER24H: read_value_out = 32'b0;
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`RV32_CSR_MHPMCOUNTER25H: read_value_out = 32'b0;
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`RV32_CSR_MHPMCOUNTER26H: read_value_out = 32'b0;
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`RV32_CSR_MHPMCOUNTER27H: read_value_out = 32'b0;
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`RV32_CSR_MHPMCOUNTER28H: read_value_out = 32'b0;
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`RV32_CSR_MHPMCOUNTER29H: read_value_out = 32'b0;
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`RV32_CSR_MHPMCOUNTER30H: read_value_out = 32'b0;
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`RV32_CSR_MHPMCOUNTER31H: read_value_out = 32'b0;
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`RV32_CSR_CYCLE: read_value_out = cycle[31:0];
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`RV32_CSR_TIME: read_value_out = cycle[31:0];
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`RV32_CSR_INSTRET: read_value_out = instret[31:0];
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`RV32_CSR_CYCLEH: read_value_out = cycle[63:32];
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`RV32_CSR_TIMEH: read_value_out = cycle[63:32];
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`RV32_CSR_INSTRETH: read_value_out = instret[63:32];
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`RV32_CSR_MVENDORID: read_value_out = 32'b0;
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`RV32_CSR_MARCHID: read_value_out = 32'b0;
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`RV32_CSR_MIMPID: read_value_out = 32'b0;
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`RV32_CSR_MHARTID: read_value_out = 32'b0;
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default: read_value_out = 32'bx;
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endcase
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case (write_op_in)
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