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Add memory address decoding

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This commit is contained in:
Graham Edgecombe 2017-12-06 08:01:51 +00:00
parent cc1f73e19e
commit 0be0da3917
2 changed files with 21 additions and 11 deletions
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24
ram.sv
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@ -5,6 +5,7 @@ module ram (
input clk,
/* control in */
input sel_in,
input [3:0] write_mask_in,
/* data in */
@ -15,21 +16,26 @@ module ram (
output [31:0] read_value_out
);
logic [31:0] mem [2047:0];
logic [31:0] read_value;
assign read_value_out = sel_in ? read_value : 0;
always_ff @(negedge clk) begin
read_value_out <= mem[address_in[31:2]];
read_value <= mem[address_in[31:2]];
if (write_mask_in[3])
mem[address_in[31:2]][31:24] <= write_value_in[31:24];
if (sel_in) begin
if (write_mask_in[3])
mem[address_in[31:2]][31:24] <= write_value_in[31:24];
if (write_mask_in[2])
mem[address_in[31:2]][23:16] <= write_value_in[23:16];
if (write_mask_in[2])
mem[address_in[31:2]][23:16] <= write_value_in[23:16];
if (write_mask_in[1])
mem[address_in[31:2]][15:8] <= write_value_in[15:8];
if (write_mask_in[1])
mem[address_in[31:2]][15:8] <= write_value_in[15:8];
if (write_mask_in[0])
mem[address_in[31:2]][7:0] <= write_value_in[7:0];
if (write_mask_in[0])
mem[address_in[31:2]][7:0] <= write_value_in[7:0];
end
end
endmodule

8
top.sv
View file

@ -64,13 +64,17 @@ module top (
/* memory bus data */
logic [31:0] mem_address;
logic [31:0] mem_read_value;
logic [31:0] mem_read_value = ram_read_value;
logic [31:0] mem_write_value;
logic ram_sel = mem_address[31:16] == 0;
logic [31:0] ram_read_value;
ram ram (
.clk(clk_slow),
/* control in */
.sel_in(ram_sel),
.write_mask_in(mem_write_mask),
/* data in */
@ -78,6 +82,6 @@ module top (
.write_value_in(mem_write_value),
/* data out */
.read_value_out(mem_read_value)
.read_value_out(ram_read_value)
);
endmodule