Pass -full to opt

Reduces the number of LUTs slightly.
This commit is contained in:
Graham Edgecombe 2017-12-08 22:29:22 +00:00
parent 02a742b3c9
commit bf7b1bef4f

2
top.ys
View file

@ -1,6 +1,6 @@
read_verilog -noautowire -sv top.sv
proc
opt
opt -full
alumacc
share -aggressive
synth_ice40 -abc2 -top top -blif top.blif