Revert "Reset {rs1,rs2_out} when flushing the decode stage"
This reverts commit 144cbe996fab0596230d9b7d14c94373e8e5bbba. It isn't required as we reset the rd_writeback_out register.
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@ -496,8 +496,6 @@ module rv32_decode (
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endcase
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if (flush_in) begin
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rs1_out <= 0;
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rs2_out <= 0;
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mem_read_en_out <= 0;
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mem_write_en_out <= 0;
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branch_op_out <= RV32_BRANCH_OP_NEVER;
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