32-bit RISC-V system on chip for iCE40 FPGAs

Graham Edgecombe 9541f198c2 Revert "Reset {rs1,rs2_out} when flushing the decode stage" ... This reverts commit 144cbe996fab0596230d9b7d14c94373e8e5bbba. It isn't required as we reset the rd_writeback_out register.		2017-12-07 22:37:58 +00:00
.gitignore	Populate instr_mem with a test assembly program	2017-12-02 18:07:37 +00:00
clk_div.sv	Replace wire with logic	2017-12-07 22:37:58 +00:00
ice40hx8k-b-evn.pcf	Add serial flash, LED and UART pins	2017-12-01 23:25:06 +00:00
Makefile	Populate instr_mem with a test assembly program	2017-12-02 18:07:37 +00:00
progmem.s	Use 4 space indentation in the assembly file for consistency	2017-12-07 22:37:58 +00:00
rv32.sv	Fix load-use hazard logic	2017-12-07 22:37:58 +00:00
rv32_alu.sv	Remove _ops.sv files	2017-12-07 22:37:58 +00:00
rv32_branch.sv	Remove _ops.sv files	2017-12-07 22:37:58 +00:00
rv32_decode.sv	Revert "Reset {rs1,rs2_out} when flushing the decode stage"	2017-12-07 22:37:58 +00:00
rv32_execute.sv	Pass forwarded rs1 value to the branch target mux	2017-12-07 22:37:58 +00:00
rv32_fetch.sv	Follow the standard naming/commenting conventions in hazard-related code	2017-12-07 22:37:58 +00:00
rv32_hazard.sv	Fix load-use hazard logic	2017-12-07 22:37:58 +00:00
rv32_mem.sv	Remove _ops.sv files	2017-12-07 22:37:58 +00:00
rv32_opcodes.sv	Add flush and stall inputs to every stage	2017-12-07 22:37:58 +00:00
rv32_regs.sv	Follow the standard naming/commenting conventions in hazard-related code	2017-12-07 22:37:58 +00:00
top.sv	Add clock divider	2017-12-07 22:37:58 +00:00
top.ys	Run abc twice to improve logic density	2017-12-07 22:37:58 +00:00