Replace wire with logic

clk_div.sv

@@ -7,7 +7,7 @@ module clk_div #(
     input clk_in,
     output clk_out
 );
-    wire [LOG_DIVISOR-1:0] q;
+    logic [LOG_DIVISOR-1:0] q;
 
     always_ff @(posedge clk_in)
         q <= q + 1;

rv32_branch.sv

@@ -33,7 +33,7 @@ module rv32_branch (
     /* control out */
     output taken_out
 );
-    wire non_zero = |result_in;
+    logic non_zero = |result_in;
 
     always_comb begin
         case (op_in)