pingu_98/icicle
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

Rename rd_writeback to rd_write

Browse source 
This is consistent with the mem_read and mem_write naming.
This commit is contained in:
Graham Edgecombe 2017-12-06 14:53:42 +00:00
parent 36b7d33850
commit 460159a392
6 changed files with 61 additions and 61 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

22
rv32.sv
View file

@ -27,7 +27,7 @@ module rv32 (
.decode_mem_read_in(decode_mem_read),
.decode_rd_in(decode_rd),
.decode_rd_writeback_in(decode_rd_writeback),
.decode_rd_write_in(decode_rd_write),
.mem_branch_taken_in(mem_branch_taken),
@ -92,7 +92,7 @@ module rv32 (
/* control in (from writeback) */
.rd_in(mem_rd),
.rd_writeback_in(mem_rd_writeback),
.rd_write_in(mem_rd_write),
/* data in */
.pc_in(fetch_pc),
@ -119,7 +119,7 @@ module rv32 (
.branch_op_out(decode_branch_op),
.branch_pc_src_out(decode_branch_pc_src),
.rd_out(decode_rd),
.rd_writeback_out(decode_rd_writeback),
.rd_write_out(decode_rd_write),
/* data out */
.pc_out(decode_pc),
@ -146,7 +146,7 @@ module rv32 (
logic [1:0] decode_branch_op;
logic decode_branch_pc_src;
logic [4:0] decode_rd;
logic decode_rd_writeback;
logic decode_rd_write;
/* decode -> execute data */
logic [31:0] decode_pc;
@ -175,11 +175,11 @@ module rv32 (
.branch_op_in(decode_branch_op),
.branch_pc_src_in(decode_branch_pc_src),
.rd_in(decode_rd),
.rd_writeback_in(decode_rd_writeback),
.rd_write_in(decode_rd_write),
/* control in (from writeback) */
.writeback_rd_in(mem_rd),
.writeback_rd_writeback_in(mem_rd_writeback),
.writeback_rd_write_in(mem_rd_write),
/* data in */
.pc_in(decode_pc),
@ -197,7 +197,7 @@ module rv32 (
.mem_zero_extend_out(execute_mem_zero_extend),
.branch_op_out(execute_branch_op),
.rd_out(execute_rd),
.rd_writeback_out(execute_rd_writeback),
.rd_write_out(execute_rd_write),
/* data out */
.result_out(execute_result),
@ -212,7 +212,7 @@ module rv32 (
logic execute_mem_zero_extend;
logic [1:0] execute_branch_op;
logic [4:0] execute_rd;
logic execute_rd_writeback;
logic execute_rd_write;
/* execute -> mem data */
logic [31:0] execute_result;
@ -233,7 +233,7 @@ module rv32 (
.zero_extend_in(execute_mem_zero_extend),
.branch_op_in(execute_branch_op),
.rd_in(execute_rd),
.rd_writeback_in(execute_rd_writeback),
.rd_write_in(execute_rd_write),
/* data in */
.result_in(execute_result),
@ -246,7 +246,7 @@ module rv32 (
/* control out */
.branch_taken_out(mem_branch_taken),
.rd_out(mem_rd),
.rd_writeback_out(mem_rd_writeback),
.rd_write_out(mem_rd_write),
/* control out (to memory bus) */
.write_mask_out(write_mask_out),
@ -262,7 +262,7 @@ module rv32 (
/* mem -> writeback control */
logic [4:0] mem_rd;
logic mem_rd_writeback;
logic mem_rd_write;
/* mem -> fetch control */
logic mem_branch_taken;

66
rv32_decode.sv
View file

@ -16,7 +16,7 @@ module rv32_decode (
/* control in (from writeback) */
input [4:0] rd_in,
input rd_writeback_in,
input rd_write_in,
/* data in */
input [31:0] pc_in,
@ -44,7 +44,7 @@ module rv32_decode (
output [1:0] branch_op_out,
output branch_pc_src_out,
output [4:0] rd_out,
output rd_writeback_out,
output rd_write_out,
/* data out */
output [31:0] pc_out,
@ -80,7 +80,7 @@ module rv32_decode (
.rs1_in(rs1),
.rs2_in(rs2),
.rd_in(rd_in),
.rd_writeback_in(rd_writeback_in),
.rd_write_in(rd_write_in),
/* data in */
.rd_value_in(rd_value_in),
@ -106,7 +106,7 @@ module rv32_decode (
branch_op_out <= RV32_BRANCH_OP_NEVER;
branch_pc_src_out <= 1'bx;
rd_out <= rd;
rd_writeback_out <= 0;
rd_write_out <= 0;
pc_out <= pc_in;
imm_out <= 32'bx;
@ -117,7 +117,7 @@ module rv32_decode (
valid_out <= 1;
alu_op_out <= RV32_ALU_OP_SRC2;
alu_src2_out <= RV32_ALU_SRC2_IMM;
rd_writeback_out <= 1;
rd_write_out <= 1;
imm_out <= imm_u;
end
{RV32_OPCODE_AUIPC, RV32_FUNCT3_ANY, RV32_FUNCT7_ANY}: begin
@ -127,7 +127,7 @@ module rv32_decode (
alu_sub_sra_out <= 0;
alu_src1_out <= RV32_ALU_SRC1_PC;
alu_src2_out <= RV32_ALU_SRC2_IMM;
rd_writeback_out <= 1;
rd_write_out <= 1;
imm_out <= imm_u;
end
{RV32_OPCODE_JAL, RV32_FUNCT3_ANY, RV32_FUNCT7_ANY}: begin
@ -137,7 +137,7 @@ module rv32_decode (
alu_src1_out <= RV32_ALU_SRC1_PC;
branch_op_out <= RV32_BRANCH_OP_ALWAYS;
branch_pc_src_out <= RV32_BRANCH_PC_SRC_IMM;
rd_writeback_out <= 1;
rd_write_out <= 1;
imm_out <= imm_j;
end
{RV32_OPCODE_JALR, RV32_FUNCT3_ZERO, RV32_FUNCT7_ANY}: begin
@ -147,7 +147,7 @@ module rv32_decode (
alu_src1_out <= RV32_ALU_SRC1_PC;
branch_op_out <= RV32_BRANCH_OP_ALWAYS;
branch_pc_src_out <= RV32_BRANCH_PC_SRC_REG;
rd_writeback_out <= 1;
rd_write_out <= 1;
imm_out <= imm_i;
end
{RV32_OPCODE_BRANCH, RV32_FUNCT3_BRANCH_BEQ, RV32_FUNCT7_ANY}: begin
@ -226,7 +226,7 @@ module rv32_decode (
mem_read_out <= 1;
mem_width_out <= RV32_MEM_WIDTH_BYTE;
mem_zero_extend_out <= 0;
rd_writeback_out <= 1;
rd_write_out <= 1;
imm_out <= imm_i;
end
{RV32_OPCODE_LOAD, RV32_FUNCT3_LOAD_LH, RV32_FUNCT7_ANY}: begin
@ -239,7 +239,7 @@ module rv32_decode (
mem_read_out <= 1;
mem_width_out <= RV32_MEM_WIDTH_HALF;
mem_zero_extend_out <= 0;
rd_writeback_out <= 1;
rd_write_out <= 1;
imm_out <= imm_i;
end
{RV32_OPCODE_LOAD, RV32_FUNCT3_LOAD_LW, RV32_FUNCT7_ANY}: begin
@ -251,7 +251,7 @@ module rv32_decode (
alu_src2_out <= RV32_ALU_SRC2_IMM;
mem_read_out <= 1;
mem_width_out <= RV32_MEM_WIDTH_WORD;
rd_writeback_out <= 1;
rd_write_out <= 1;
imm_out <= imm_i;
end
{RV32_OPCODE_LOAD, RV32_FUNCT3_LOAD_LBU, RV32_FUNCT7_ANY}: begin
@ -264,7 +264,7 @@ module rv32_decode (
mem_read_out <= 1;
mem_width_out <= RV32_MEM_WIDTH_BYTE;
mem_zero_extend_out <= 1;
rd_writeback_out <= 1;
rd_write_out <= 1;
imm_out <= imm_i;
end
{RV32_OPCODE_LOAD, RV32_FUNCT3_LOAD_LHU, RV32_FUNCT7_ANY}: begin
@ -277,7 +277,7 @@ module rv32_decode (
mem_read_out <= 1;
mem_width_out <= RV32_MEM_WIDTH_HALF;
mem_zero_extend_out <= 1;
rd_writeback_out <= 1;
rd_write_out <= 1;
imm_out <= imm_i;
end
{RV32_OPCODE_STORE, RV32_FUNCT3_STORE_SB, RV32_FUNCT7_ANY}: begin
@ -320,7 +320,7 @@ module rv32_decode (
alu_sub_sra_out <= 0;
alu_src1_out <= RV32_ALU_SRC1_REG;
alu_src2_out <= RV32_ALU_SRC2_IMM;
rd_writeback_out <= 1;
rd_write_out <= 1;
imm_out <= imm_i;
end
{RV32_OPCODE_OP_IMM, RV32_FUNCT3_OP_SLT, RV32_FUNCT7_ANY}: begin
@ -330,7 +330,7 @@ module rv32_decode (
alu_sub_sra_out <= 1;
alu_src1_out <= RV32_ALU_SRC1_REG;
alu_src2_out <= RV32_ALU_SRC2_IMM;
rd_writeback_out <= 1;
rd_write_out <= 1;
imm_out <= imm_i;
end
{RV32_OPCODE_OP_IMM, RV32_FUNCT3_OP_SLTU, RV32_FUNCT7_ANY}: begin
@ -340,7 +340,7 @@ module rv32_decode (
alu_sub_sra_out <= 1;
alu_src1_out <= RV32_ALU_SRC1_REG;
alu_src2_out <= RV32_ALU_SRC2_IMM;
rd_writeback_out <= 1;
rd_write_out <= 1;
imm_out <= imm_i;
end
{RV32_OPCODE_OP_IMM, RV32_FUNCT3_OP_XOR, RV32_FUNCT7_ANY}: begin
@ -349,7 +349,7 @@ module rv32_decode (
alu_op_out <= RV32_ALU_OP_XOR;
alu_src1_out <= RV32_ALU_SRC1_REG;
alu_src2_out <= RV32_ALU_SRC2_IMM;
rd_writeback_out <= 1;
rd_write_out <= 1;
imm_out <= imm_i;
end
{RV32_OPCODE_OP_IMM, RV32_FUNCT3_OP_OR, RV32_FUNCT7_ANY}: begin
@ -358,7 +358,7 @@ module rv32_decode (
alu_op_out <= RV32_ALU_OP_OR;
alu_src1_out <= RV32_ALU_SRC1_REG;
alu_src2_out <= RV32_ALU_SRC2_IMM;
rd_writeback_out <= 1;
rd_write_out <= 1;
imm_out <= imm_i;
end
{RV32_OPCODE_OP_IMM, RV32_FUNCT3_OP_AND, RV32_FUNCT7_ANY}: begin
@ -367,7 +367,7 @@ module rv32_decode (
alu_op_out <= RV32_ALU_OP_AND;
alu_src1_out <= RV32_ALU_SRC1_REG;
alu_src2_out <= RV32_ALU_SRC2_IMM;
rd_writeback_out <= 1;
rd_write_out <= 1;
imm_out <= imm_i;
end
{RV32_OPCODE_OP_IMM, RV32_FUNCT3_OP_SLL, RV32_FUNCT7_ZERO}: begin
@ -376,7 +376,7 @@ module rv32_decode (
alu_op_out <= RV32_ALU_OP_SLL;
alu_src1_out <= RV32_ALU_SRC1_REG;
alu_src2_out <= RV32_ALU_SRC2_IMM;
rd_writeback_out <= 1;
rd_write_out <= 1;
imm_out <= shamt;
end
{RV32_OPCODE_OP_IMM, RV32_FUNCT3_OP_SRL_SRA, RV32_FUNCT7_ZERO}: begin
@ -386,7 +386,7 @@ module rv32_decode (
alu_sub_sra_out <= 0;
alu_src1_out <= RV32_ALU_SRC1_REG;
alu_src2_out <= RV32_ALU_SRC2_IMM;
rd_writeback_out <= 1;
rd_write_out <= 1;
imm_out <= shamt;
end
{RV32_OPCODE_OP_IMM, RV32_FUNCT3_OP_SRL_SRA, RV32_FUNCT7_OP_SRA}: begin
@ -396,7 +396,7 @@ module rv32_decode (
alu_sub_sra_out <= 1;
alu_src1_out <= RV32_ALU_SRC1_REG;
alu_src2_out <= RV32_ALU_SRC2_IMM;
rd_writeback_out <= 1;
rd_write_out <= 1;
imm_out <= shamt;
end
{RV32_OPCODE_OP, RV32_FUNCT3_OP_ADD_SUB, RV32_FUNCT7_ZERO}: begin
@ -406,7 +406,7 @@ module rv32_decode (
alu_sub_sra_out <= 0;
alu_src1_out <= RV32_ALU_SRC1_REG;
alu_src2_out <= RV32_ALU_SRC2_REG;
rd_writeback_out <= 1;
rd_write_out <= 1;
end
{RV32_OPCODE_OP, RV32_FUNCT3_OP_ADD_SUB, RV32_FUNCT7_OP_SUB}: begin
/* SUB */
@ -415,7 +415,7 @@ module rv32_decode (
alu_sub_sra_out <= 1;
alu_src1_out <= RV32_ALU_SRC1_REG;
alu_src2_out <= RV32_ALU_SRC2_REG;
rd_writeback_out <= 1;
rd_write_out <= 1;
end
{RV32_OPCODE_OP, RV32_FUNCT3_OP_SLL, RV32_FUNCT7_ZERO}: begin
/* SLL */
@ -423,7 +423,7 @@ module rv32_decode (
alu_op_out <= RV32_ALU_OP_SLL;
alu_src1_out <= RV32_ALU_SRC1_REG;
alu_src2_out <= RV32_ALU_SRC2_REG;
rd_writeback_out <= 1;
rd_write_out <= 1;
end
{RV32_OPCODE_OP, RV32_FUNCT3_OP_SLT, RV32_FUNCT7_ZERO}: begin
/* SLT */
@ -432,7 +432,7 @@ module rv32_decode (
alu_sub_sra_out <= 1;
alu_src1_out <= RV32_ALU_SRC1_REG;
alu_src2_out <= RV32_ALU_SRC2_REG;
rd_writeback_out <= 1;
rd_write_out <= 1;
end
{RV32_OPCODE_OP, RV32_FUNCT3_OP_SLTU, RV32_FUNCT7_ZERO}: begin
/* SLTU */
@ -441,7 +441,7 @@ module rv32_decode (
alu_sub_sra_out <= 1;
alu_src1_out <= RV32_ALU_SRC1_REG;
alu_src2_out <= RV32_ALU_SRC2_REG;
rd_writeback_out <= 1;
rd_write_out <= 1;
end
{RV32_OPCODE_OP, RV32_FUNCT3_OP_XOR, RV32_FUNCT7_ZERO}: begin
/* XOR */
@ -449,7 +449,7 @@ module rv32_decode (
alu_op_out <= RV32_ALU_OP_XOR;
alu_src1_out <= RV32_ALU_SRC1_REG;
alu_src2_out <= RV32_ALU_SRC2_REG;
rd_writeback_out <= 1;
rd_write_out <= 1;
end
{RV32_OPCODE_OP, RV32_FUNCT3_OP_SRL_SRA, RV32_FUNCT7_ZERO}: begin
/* SRL */
@ -458,7 +458,7 @@ module rv32_decode (
alu_sub_sra_out <= 0;
alu_src1_out <= RV32_ALU_SRC1_REG;
alu_src2_out <= RV32_ALU_SRC2_REG;
rd_writeback_out <= 1;
rd_write_out <= 1;
end
{RV32_OPCODE_OP, RV32_FUNCT3_OP_SRL_SRA, RV32_FUNCT7_OP_SRA}: begin
/* SRA */
@ -467,7 +467,7 @@ module rv32_decode (
alu_sub_sra_out <= 1;
alu_src1_out <= RV32_ALU_SRC1_REG;
alu_src2_out <= RV32_ALU_SRC2_REG;
rd_writeback_out <= 1;
rd_write_out <= 1;
end
{RV32_OPCODE_OP, RV32_FUNCT3_OP_OR, RV32_FUNCT7_ZERO}: begin
/* OR */
@ -475,7 +475,7 @@ module rv32_decode (
alu_op_out <= RV32_ALU_OP_OR;
alu_src1_out <= RV32_ALU_SRC1_REG;
alu_src2_out <= RV32_ALU_SRC2_REG;
rd_writeback_out <= 1;
rd_write_out <= 1;
end
{RV32_OPCODE_OP, RV32_FUNCT3_OP_AND, RV32_FUNCT7_ZERO}: begin
/* AND */
@ -483,7 +483,7 @@ module rv32_decode (
alu_op_out <= RV32_ALU_OP_AND;
alu_src1_out <= RV32_ALU_SRC1_REG;
alu_src2_out <= RV32_ALU_SRC2_REG;
rd_writeback_out <= 1;
rd_write_out <= 1;
end
{RV32_OPCODE_MISC_MEM, RV32_FUNCT3_MISC_MEM_FENCE, RV32_FUNCT7_ANY}: begin
/* FENCE */
@ -499,7 +499,7 @@ module rv32_decode (
mem_read_out <= 0;
mem_write_out <= 0;
branch_op_out <= RV32_BRANCH_OP_NEVER;
rd_writeback_out <= 0;
rd_write_out <= 0;
end
end
end

18
rv32_execute.sv
View file

@ -25,11 +25,11 @@ module rv32_execute (
input [1:0] branch_op_in,
input branch_pc_src_in,
input [4:0] rd_in,
input rd_writeback_in,
input rd_write_in,
/* control in (from writeback) */
input [4:0] writeback_rd_in,
input writeback_rd_writeback_in,
input writeback_rd_write_in,
/* data in */
input [31:0] pc_in,
@ -47,7 +47,7 @@ module rv32_execute (
output mem_zero_extend_out,
output [1:0] branch_op_out,
output [4:0] rd_out,
output rd_writeback_out,
output rd_write_out,
/* data out */
output [31:0] result_out,
@ -58,16 +58,16 @@ module rv32_execute (
logic [31:0] rs2_value;
always_comb begin
if (rd_writeback_out && rd_out == rs1_in && |rs1_in)
if (rd_write_out && rd_out == rs1_in && |rs1_in)
rs1_value = result_out;
else if (writeback_rd_writeback_in && writeback_rd_in == rs1_in && |rs1_in)
else if (writeback_rd_write_in && writeback_rd_in == rs1_in && |rs1_in)
rs1_value = writeback_rd_value_in;
else
rs1_value = rs1_value_in;
if (rd_writeback_out && rd_out == rs2_in && |rs2_in)
if (rd_write_out && rd_out == rs2_in && |rs2_in)
rs2_value = result_out;
else if (writeback_rd_writeback_in && writeback_rd_in == rs2_in && |rs2_in)
else if (writeback_rd_write_in && writeback_rd_in == rs2_in && |rs2_in)
rs2_value = writeback_rd_value_in;
else
rs2_value = rs2_value_in;
@ -115,7 +115,7 @@ module rv32_execute (
mem_zero_extend_out <= mem_zero_extend_in;
branch_op_out <= branch_op_in;
rd_out <= rd_in;
rd_writeback_out <= rd_writeback_in;
rd_write_out <= rd_write_in;
result_out <= result;
rs2_value_out <= rs2_value;
branch_pc_out <= branch_pc;
@ -124,7 +124,7 @@ module rv32_execute (
mem_read_out <= 0;
mem_write_out <= 0;
branch_op_out <= RV32_BRANCH_OP_NEVER;
rd_writeback_out <= 0;
rd_write_out <= 0;
end
end
end

4
rv32_hazard.sv
View file

@ -8,7 +8,7 @@ module rv32_hazard (
input decode_mem_read_in,
input [4:0] decode_rd_in,
input decode_rd_writeback_in,
input decode_rd_write_in,
input mem_branch_taken_in,
@ -25,7 +25,7 @@ module rv32_hazard (
output mem_stall_out,
output mem_flush_out
);
logic fetch_wait_for_mem_read = (decode_rs1_in == decode_rd_in || decode_rs2_in == decode_rd_in) && |decode_rd_in && decode_mem_read_in && decode_rd_writeback_in;
logic fetch_wait_for_mem_read = (decode_rs1_in == decode_rd_in || decode_rs2_in == decode_rd_in) && |decode_rd_in && decode_mem_read_in && decode_rd_write_in;
assign fetch_stall_out = decode_stall_out || fetch_wait_for_mem_read;
assign fetch_flush_out = 0;

8
rv32_mem.sv
View file

@ -21,7 +21,7 @@ module rv32_mem (
input zero_extend_in,
input [1:0] branch_op_in,
input [4:0] rd_in,
input rd_writeback_in,
input rd_write_in,
/* data in */
input [31:0] result_in,
@ -34,7 +34,7 @@ module rv32_mem (
/* control out */
output branch_taken_out,
output [4:0] rd_out,
output rd_writeback_out,
output rd_write_out,
/* control out (to memory bus) */
output [3:0] write_mask_out,
@ -115,7 +115,7 @@ module rv32_mem (
always_ff @(posedge clk) begin
if (!stall_in) begin
rd_out <= rd_in;
rd_writeback_out <= rd_writeback_in;
rd_write_out <= rd_write_in;
if (read_in) begin
case (width_in)
@ -145,7 +145,7 @@ module rv32_mem (
end
if (flush_in)
rd_writeback_out <= 0;
rd_write_out <= 0;
end
end
endmodule

4
rv32_regs.sv
View file

@ -9,7 +9,7 @@ module rv32_regs (
input [4:0] rs1_in,
input [4:0] rs2_in,
input [4:0] rd_in,
input rd_writeback_in,
input rd_write_in,
/* data in */
input [31:0] rd_value_in,
@ -26,7 +26,7 @@ module rv32_regs (
rs2_value_out <= regs[rs2_in];
end
if (rd_writeback_in && |rd_in)
if (rd_write_in && |rd_in)
regs[rd_in] <= rd_value_in;
end
endmodule