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Prefix data bus wire names with data_

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This commit is contained in:
Graham Edgecombe 2017-12-17 19:57:00 +00:00
parent b01e81357d
commit 7ef3e831ce
3 changed files with 51 additions and 51 deletions
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22
rv32.sv
View file

@ -10,12 +10,12 @@
module rv32 (
input clk,
/* memory bus */
output logic [31:0] address_out,
output logic read_out,
input [31:0] read_value_in,
output logic [3:0] write_mask_out,
output logic [31:0] write_value_out
/* data memory bus */
output logic [31:0] data_address_out,
output logic data_read_out,
input [31:0] data_read_value_in,
output logic [3:0] data_write_mask_out,
output logic [31:0] data_write_value_out
);
/* hazard -> fetch control */
logic fetch_stall;
@ -251,7 +251,7 @@ module rv32 (
.branch_pc_in(execute_branch_pc),
/* data in (from memory bus) */
.read_value_in(read_value_in),
.data_read_value_in(data_read_value_in),
/* control out */
.branch_taken_out(mem_branch_taken),
@ -259,16 +259,16 @@ module rv32 (
.rd_write_out(mem_rd_write),
/* control out (to memory bus) */
.read_out(read_out),
.write_mask_out(write_mask_out),
.data_read_out(data_read_out),
.data_write_mask_out(data_write_mask_out),
/* data out */
.rd_value_out(mem_rd_value),
.branch_pc_out(mem_branch_pc),
/* data out (to memory bus) */
.address_out(address_out),
.write_value_out(write_value_out)
.data_address_out(data_address_out),
.data_write_value_out(data_write_value_out)
);
endmodule

70
rv32_mem.sv
View file

@ -28,25 +28,25 @@ module rv32_mem (
input [31:0] rs2_value_in,
input [31:0] branch_pc_in,
/* data in (from memory bus) */
input [31:0] read_value_in,
/* data in (from data memory bus) */
input [31:0] data_read_value_in,
/* control out */
output logic branch_taken_out,
output logic [4:0] rd_out,
output logic rd_write_out,
/* control out (to memory bus) */
output logic read_out,
output logic [3:0] write_mask_out,
/* control out (to data memory bus) */
output logic data_read_out,
output logic [3:0] data_write_mask_out,
/* data out */
output logic [31:0] rd_value_out,
output logic [31:0] branch_pc_out,
/* data out (to memory bus) */
output logic [31:0] address_out,
output logic [31:0] write_value_out
/* data out (to data memory bus) */
output logic [31:0] data_address_out,
output logic [31:0] data_write_value_out
);
rv32_branch_unit branch_unit (
/* control in */
@ -61,56 +61,56 @@ module rv32_mem (
assign branch_pc_out = branch_pc_in;
assign read_out = read_in;
assign address_out = result_in;
assign data_read_out = read_in;
assign data_address_out = result_in;
always_comb begin
if (write_in) begin
case (width_in)
`RV32_MEM_WIDTH_WORD: begin
write_value_out = rs2_value_in;
write_mask_out = 4'b1111;
data_write_value_out = rs2_value_in;
data_write_mask_out = 4'b1111;
end
`RV32_MEM_WIDTH_HALF: begin
case (result_in[0])
2'b0: begin
write_value_out = {rs2_value_in[15:0], 16'bx};
write_mask_out = 4'b1100;
data_write_value_out = {rs2_value_in[15:0], 16'bx};
data_write_mask_out = 4'b1100;
end
2'b1: begin
write_value_out = {16'bx, rs2_value_in[15:0]};
write_mask_out = 4'b0011;
data_write_value_out = {16'bx, rs2_value_in[15:0]};
data_write_mask_out = 4'b0011;
end
endcase
end
`RV32_MEM_WIDTH_BYTE: begin
case (result_in[1:0])
2'b00: begin
write_value_out = {rs2_value_in[7:0], 24'bx};
write_mask_out = 4'b1000;
data_write_value_out = {rs2_value_in[7:0], 24'bx};
data_write_mask_out = 4'b1000;
end
2'b01: begin
write_value_out = {8'bx, rs2_value_in[7:0], 16'bx};
write_mask_out = 4'b0100;
data_write_value_out = {8'bx, rs2_value_in[7:0], 16'bx};
data_write_mask_out = 4'b0100;
end
2'b10: begin
write_value_out = {16'bx, rs2_value_in[7:0], 8'bx};
write_mask_out = 4'b0010;
data_write_value_out = {16'bx, rs2_value_in[7:0], 8'bx};
data_write_mask_out = 4'b0010;
end
2'b11: begin
write_value_out = {24'bx, rs2_value_in[7:0]};
write_mask_out = 4'b0001;
data_write_value_out = {24'bx, rs2_value_in[7:0]};
data_write_mask_out = 4'b0001;
end
endcase
end
default: begin
write_value_out = 32'bx;
write_mask_out = 4'bx;
data_write_value_out = 32'bx;
data_write_mask_out = 4'bx;
end
endcase
end else begin
write_value_out = 32'bx;
write_mask_out = 4'b0;
data_write_value_out = 32'bx;
data_write_mask_out = 4'b0;
end
end
@ -122,20 +122,20 @@ module rv32_mem (
if (read_in) begin
case (width_in)
`RV32_MEM_WIDTH_WORD: begin
rd_value_out <= read_value_in;
rd_value_out <= data_read_value_in;
end
`RV32_MEM_WIDTH_HALF: begin
case (result_in[0])
1'b0: rd_value_out <= {{16{zero_extend_in ? 1'b0 : read_value_in[31]}}, read_value_in[31:16]};
1'b1: rd_value_out <= {{16{zero_extend_in ? 1'b0 : read_value_in[15]}}, read_value_in[15:0]};
1'b0: rd_value_out <= {{16{zero_extend_in ? 1'b0 : data_read_value_in[31]}}, data_read_value_in[31:16]};
1'b1: rd_value_out <= {{16{zero_extend_in ? 1'b0 : data_read_value_in[15]}}, data_read_value_in[15:0]};
endcase
end
`RV32_MEM_WIDTH_BYTE: begin
case (result_in[1:0])
2'b00: rd_value_out <= {{24{zero_extend_in ? 1'b0 : read_value_in[31]}}, read_value_in[31:24]};
2'b01: rd_value_out <= {{24{zero_extend_in ? 1'b0 : read_value_in[23]}}, read_value_in[23:16]};
2'b10: rd_value_out <= {{24{zero_extend_in ? 1'b0 : read_value_in[15]}}, read_value_in[15:8]};
2'b11: rd_value_out <= {{24{zero_extend_in ? 1'b0 : read_value_in[7]}}, read_value_in[7:0]};
2'b00: rd_value_out <= {{24{zero_extend_in ? 1'b0 : data_read_value_in[31]}}, data_read_value_in[31:24]};
2'b01: rd_value_out <= {{24{zero_extend_in ? 1'b0 : data_read_value_in[23]}}, data_read_value_in[23:16]};
2'b10: rd_value_out <= {{24{zero_extend_in ? 1'b0 : data_read_value_in[15]}}, data_read_value_in[15:8]};
2'b11: rd_value_out <= {{24{zero_extend_in ? 1'b0 : data_read_value_in[7]}}, data_read_value_in[7:0]};
endcase
end
default: begin

10
top.sv
View file

@ -70,11 +70,11 @@ module top (
.clk(pll_clk),
/* memory bus */
.address_out(mem_address),
.read_out(mem_read),
.read_value_in(mem_read_value),
.write_mask_out(mem_write_mask),
.write_value_out(mem_write_value)
.data_address_out(mem_address),
.data_read_out(mem_read),
.data_read_value_in(mem_read_value),
.data_write_mask_out(mem_write_mask),
.data_write_value_out(mem_write_value)
);
always_comb begin