Fix TX ready output

2017-12-07 20:22:11 +00:00 · 2017-12-07 20:22:11 +00:00 · 4d9d405c05
commit 4d9d405c05
parent 6d638404f1
1 changed files with 1 additions and 1 deletions
--- a/uart.sv
+++ b/uart.sv
@ -43,7 +43,7 @@ module uart (
                    read_value_out = {16'b0, clk_div};
                end
                UART_REG_STATUS: begin
-                    read_value_out = {31'b0, |tx_bits};
+                    read_value_out = {31'b0, ~|tx_bits};
                end
                UART_REG_DATA: begin
                    read_value_out = 0;