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Implement FENCE.I

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This commit is contained in:
Graham Edgecombe 2017-12-27 15:23:59 +00:00
parent 0013935bb0
commit de1f936cdd
3 changed files with 23 additions and 5 deletions
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13
rv32.sv
View file

@ -48,6 +48,7 @@ module rv32 (
/* decode -> hazard control */
logic [4:0] decode_rs1_unreg;
logic [4:0] decode_rs2_unreg;
logic decode_mem_fence_unreg;
/* decode -> execute control */
logic [4:0] decode_rs1;
@ -102,13 +103,17 @@ module rv32 (
rv32_hazard_unit hazard_unit (
/* control in */
.decode_rs1_in(decode_rs1_unreg),
.decode_rs2_in(decode_rs2_unreg),
.decode_rs1_unreg_in(decode_rs1_unreg),
.decode_rs2_unreg_in(decode_rs2_unreg),
.decode_mem_fence_unreg_in(decode_mem_fence_unreg),
.decode_mem_read_in(decode_mem_read),
.decode_mem_fence_in(decode_mem_fence),
.decode_rd_in(decode_rd),
.decode_rd_write_in(decode_rd_write),
.execute_mem_fence_in(execute_mem_fence),
.mem_branch_taken_in(mem_branch_taken),
.instr_read_in(instr_read_out),
@ -180,6 +185,7 @@ module rv32 (
/* control out (to hazard) */
.rs1_unreg_out(decode_rs1_unreg),
.rs2_unreg_out(decode_rs2_unreg),
.mem_fence_unreg_out(decode_mem_fence_unreg),
/* control out */
.rs1_out(decode_rs1),
@ -192,6 +198,7 @@ module rv32 (
.mem_write_out(decode_mem_write),
.mem_width_out(decode_mem_width),
.mem_zero_extend_out(decode_mem_zero_extend),
.mem_fence_out(decode_mem_fence),
.branch_op_out(decode_branch_op),
.branch_pc_src_out(decode_branch_pc_src),
.rd_out(decode_rd),
@ -222,6 +229,7 @@ module rv32 (
.mem_write_in(decode_mem_write),
.mem_width_in(decode_mem_width),
.mem_zero_extend_in(decode_mem_zero_extend),
.mem_fence_in(decode_mem_fence),
.branch_op_in(decode_branch_op),
.branch_pc_src_in(decode_branch_pc_src),
.rd_in(decode_rd),
@ -245,6 +253,7 @@ module rv32 (
.mem_write_out(execute_mem_write),
.mem_width_out(execute_mem_width),
.mem_zero_extend_out(execute_mem_zero_extend),
.mem_fence_out(execute_mem_fence),
.branch_op_out(execute_branch_op),
.rd_out(execute_rd),
.rd_write_out(execute_rd_write),

3
rv32_decode.sv
View file

@ -25,6 +25,7 @@ module rv32_decode (
/* control out (to hazard) */
output logic [4:0] rs1_unreg_out,
output logic [4:0] rs2_unreg_out,
output logic mem_fence_unreg_out,
/* control out */
output logic [4:0] rs1_out,
@ -93,6 +94,8 @@ module rv32_decode (
logic branch_pc_src;
logic rd_write;
assign mem_fence_unreg_out = mem_fence;
rv32_control_unit control_unit (
/* data in */
.instr_in(instr_in),

12
rv32_hazard.sv
View file

@ -3,13 +3,17 @@
module rv32_hazard_unit (
/* control in */
input [4:0] decode_rs1_in,
input [4:0] decode_rs2_in,
input [4:0] decode_rs1_unreg_in,
input [4:0] decode_rs2_unreg_in,
input decode_mem_fence_unreg_in,
input decode_mem_read_in,
input decode_mem_fence_in,
input [4:0] decode_rd_in,
input decode_rd_write_in,
input execute_mem_fence_in,
input mem_branch_taken_in,
input instr_read_in,
@ -34,10 +38,12 @@ module rv32_hazard_unit (
);
logic fetch_wait_for_bus;
logic fetch_wait_for_mem_read;
logic fetch_wait_for_mem_fence;
logic mem_wait_for_bus;
assign fetch_wait_for_bus = instr_read_in && !instr_ready_in;
assign fetch_wait_for_mem_read = (decode_rs1_in == decode_rd_in || decode_rs2_in == decode_rd_in) && |decode_rd_in && decode_mem_read_in && decode_rd_write_in;
assign fetch_wait_for_mem_read = (decode_rs1_unreg_in == decode_rd_in || decode_rs2_unreg_in == decode_rd_in) && |decode_rd_in && decode_mem_read_in && decode_rd_write_in;
assign fetch_wait_for_mem_fence = decode_mem_fence_unreg_in || decode_mem_fence_in || execute_mem_fence_in;
assign mem_wait_for_bus = (data_read_in || data_write_in) && !data_ready_in;
assign fetch_stall_out = decode_stall_out || fetch_wait_for_mem_read || fetch_wait_for_bus;