8024a6075f
This reduces the amount of logic required and should speed the processor up slightly, as the critical path had moved from the execute stage to the branching logic in the mem/fetch stages.
105 lines
2.6 KiB
Systemverilog
105 lines
2.6 KiB
Systemverilog
`ifndef RV32_ALU
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`define RV32_ALU
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`define RV32_ALU_OP_ADD_SUB 3'b000
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`define RV32_ALU_OP_XOR 3'b001
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`define RV32_ALU_OP_OR 3'b010
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`define RV32_ALU_OP_AND 3'b011
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`define RV32_ALU_OP_SLL 3'b100
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`define RV32_ALU_OP_SRL_SRA 3'b101
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`define RV32_ALU_OP_SLT 3'b110
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`define RV32_ALU_OP_SLTU 3'b111
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`define RV32_ALU_SRC1_REG 2'b00
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`define RV32_ALU_SRC1_PC 2'b01
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`define RV32_ALU_SRC1_ZERO 2'b10
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`define RV32_ALU_SRC2_REG 2'b00
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`define RV32_ALU_SRC2_IMM 2'b01
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`define RV32_ALU_SRC2_FOUR 2'b10
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module rv32_alu (
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/* control in */
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input [2:0] op_in,
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input sub_sra_in,
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input [1:0] src1_in,
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input [1:0] src2_in,
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/* data in */
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input [31:0] pc_in,
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input [31:0] rs1_value_in,
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input [31:0] rs2_value_in,
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input [31:0] imm_value_in,
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/* control out */
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output logic non_zero_out,
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/* data out */
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output logic [31:0] result_out
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);
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logic [31:0] src1;
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logic [31:0] src2;
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logic src1_sign;
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logic src2_sign;
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logic [4:0] shamt;
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logic [32:0] add_sub;
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logic [31:0] srl_sra;
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logic carry;
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logic sign;
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logic ovf;
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logic lt;
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logic ltu;
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always_comb begin
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case (src1_in)
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`RV32_ALU_SRC1_REG: src1 = rs1_value_in;
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`RV32_ALU_SRC1_PC: src1 = pc_in;
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`RV32_ALU_SRC1_ZERO: src1 = 0;
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default: src1 = 32'bx;
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endcase
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case (src2_in)
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`RV32_ALU_SRC2_REG: src2 = rs2_value_in;
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`RV32_ALU_SRC2_IMM: src2 = imm_value_in;
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`RV32_ALU_SRC2_FOUR: src2 = 4;
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default: src2 = 32'bx;
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endcase
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end
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assign src1_sign = src1[31];
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assign src2_sign = src2[31];
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assign shamt = src2[4:0];
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assign add_sub = sub_sra_in ? src1 - src2 : src1 + src2;
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assign srl_sra = $signed({sub_sra_in ? src1_sign : 1'b0, src1}) >>> shamt;
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assign carry = add_sub[32];
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assign sign = add_sub[31];
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assign ovf = (!src1_sign && src2_sign && sign) || (src1_sign && !src2_sign && !sign);
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assign lt = sign != ovf;
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assign ltu = carry;
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always_comb begin
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case (op_in)
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`RV32_ALU_OP_ADD_SUB: result_out = add_sub[31:0];
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`RV32_ALU_OP_XOR: result_out = src1 ^ src2;
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`RV32_ALU_OP_OR: result_out = src1 | src2;
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`RV32_ALU_OP_AND: result_out = src1 & src2;
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`RV32_ALU_OP_SLL: result_out = src1 << shamt;
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`RV32_ALU_OP_SRL_SRA: result_out = srl_sra;
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`RV32_ALU_OP_SLT: result_out = {31'b0, lt};
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`RV32_ALU_OP_SLTU: result_out = {31'b0, ltu};
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endcase
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end
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assign non_zero_out = |result_out;
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endmodule
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`endif
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