0013935bb0
This increases the number of LUTs slightly (by ~20), as the immediate mux is now separate to the main control unit, but I think it's worth the cost. The imm output is also renamed to imm_value. This is consistent with rs1_value and rs2_value, and avoids a collision with the new imm output, which represents the type of immediate.
58 lines
1.6 KiB
Systemverilog
58 lines
1.6 KiB
Systemverilog
`ifndef RV32_IMM
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`define RV32_IMM
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`define RV32_IMM_I 3'b000
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`define RV32_IMM_S 3'b001
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`define RV32_IMM_B 3'b010
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`define RV32_IMM_U 3'b011
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`define RV32_IMM_J 3'b100
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`define RV32_IMM_SHAMT 3'b101
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`define RV32_IMM_ZIMM 3'b110
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module rv32_imm_mux (
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/* control in */
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input [2:0] imm_in,
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/* data in */
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input [31:0] instr_in,
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/* data out */
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output logic [31:0] imm_value_out
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);
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logic sign;
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logic [31:0] imm_i;
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logic [31:0] imm_s;
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logic [31:0] imm_b;
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logic [31:0] imm_u;
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logic [31:0] imm_j;
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logic [31:0] shamt;
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logic [31:0] zimm;
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assign sign = instr_in[31];
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assign imm_i = {{21{sign}}, instr_in[30:25], instr_in[24:21], instr_in[20]};
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assign imm_s = {{21{sign}}, instr_in[30:25], instr_in[11:8], instr_in[7]};
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assign imm_b = {{20{sign}}, instr_in[7], instr_in[30:25], instr_in[11:8], 1'b0};
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assign imm_u = {sign, instr_in[30:20], instr_in[19:12], 12'b0};
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assign imm_j = {{12{sign}}, instr_in[19:12], instr_in[20], instr_in[30:25], instr_in[24:21], 1'b0};
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assign shamt = {27'bx, instr_in[24:20]};
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assign zimm = {27'b0, instr_in[19:15]};
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always_comb begin
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case (imm_in)
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`RV32_IMM_I: imm_value_out = imm_i;
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`RV32_IMM_S: imm_value_out = imm_s;
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`RV32_IMM_B: imm_value_out = imm_b;
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`RV32_IMM_U: imm_value_out = imm_u;
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`RV32_IMM_J: imm_value_out = imm_j;
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`RV32_IMM_SHAMT: imm_value_out = shamt;
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`RV32_IMM_ZIMM: imm_value_out = zimm;
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default: imm_value_out = 32'bx;
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endcase
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end
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endmodule
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`endif
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