19 lines
266 B
Systemverilog
19 lines
266 B
Systemverilog
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`ifndef CLK_DIV
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`define CLK_DIV
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module clk_div #(
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parameter LOG_DIVISOR = 1
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) (
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input clk_in,
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output clk_out
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);
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wire [LOG_DIVISOR-1:0] q;
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always_ff @(posedge clk_in)
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q <= q + 1;
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assign clk_out = q[LOG_DIVISOR-1];
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endmodule
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`endif
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