Fix bit shifting by numbers greater than 1
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@ -27,7 +27,7 @@ module rv32_alu (
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logic src1_sign = src1[31];
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logic src2_sign = src2[31];
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logic shamt = src2[4:0];
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logic [4:0] shamt = src2[4:0];
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logic [32:0] add_sub = sub_sra_in ? src1 - src2 : src1 + src2;
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logic [31:0] srl_sra = $signed({sub_sra_in ? src1_sign : 1'b0, src1}) >>> shamt;
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