Replace always with always_ff

rv32_alu.sv

@@ -39,7 +39,7 @@ module rv32_alu (
     logic lt  = sign != ovf;
     logic ltu = carry;
 
-    always @(posedge clk) begin
+    always_ff @(posedge clk) begin
         case (op_in)
             RV32_ALU_OP_ADD_SUB: result_out <= add_sub[31:0];
             RV32_ALU_OP_XOR:     result_out <= src1 ^ src2;

rv32_execute.sv

@@ -71,7 +71,7 @@ module rv32_execute (
         .pc_out(branch_pc_out)
     );
 
-    always @(posedge clk) begin
+    always_ff @(posedge clk) begin
         mem_read_en_out <= mem_read_en_in;
         mem_write_en_out <= mem_write_en_in;
         branch_op_out <= branch_op_in;

rv32_mem.sv

@@ -44,7 +44,7 @@ module rv32_mem (
 
     assign branch_pc_out = branch_pc_in;
 
-    always @(posedge clk) begin
+    always_ff @(posedge clk) begin
         read_en_out <= read_en_in;
         rd_out <= rd_in;
         rd_writeback_out <= rd_writeback_in;