393 lines
15 KiB
Systemverilog
393 lines
15 KiB
Systemverilog
`ifndef RV32_DECODE
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`define RV32_DECODE
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`include "rv32_alu_ops.sv"
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`include "rv32_opcodes.sv"
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`include "rv32_regs.sv"
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module rv32_decode (
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input clk,
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/* data in */
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input [31:0] pc_in,
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input [31:0] instr_in,
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/* control out */
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output valid_out,
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output [3:0] alu_op_out,
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output alu_sub_sra_out,
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output alu_src1_out,
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output alu_src2_out,
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output mem_read_en_out,
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output mem_write_en_out,
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/* data out */
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output [31:0] pc_out,
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output [31:0] rs1_value_out,
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output [31:0] rs2_value_out,
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output [31:0] imm_out
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);
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logic [6:0] funct7 = instr_in[31:25];
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logic [4:0] rs2 = instr_in[24:20];
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logic [4:0] rs1 = instr_in[19:15];
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logic [2:0] funct3 = instr_in[14:12];
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logic [4:0] rd = instr_in[11:7];
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logic [6:0] opcode = instr_in[6:0];
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logic sign = instr_in[31];
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logic [31:0] imm_i = {{21{sign}}, instr_in[30:25], instr_in[24:21], instr_in[20]};
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logic [31:0] imm_s = {{21{sign}}, instr_in[30:25], instr_in[11:8], instr_in[7]};
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logic [31:0] imm_b = {{20{sign}}, instr_in[7], instr_in[30:25], instr_in[11:8], 1'b0};
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logic [31:0] imm_u = {sign, instr_in[30:20], instr_in[19:12], 12'b0};
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logic [31:0] imm_j = {{12{sign}}, instr_in[19:12], instr_in[20], instr_in[30:25], instr_in[24:1], 1'b0};
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logic [31:0] shamt = {27'b0, rs2};
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rv32_regs regs (
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.clk(clk),
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/* control in */
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.rs1_in(rs1),
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.rs2_in(rs2),
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/* data out */
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.rs1_value_out(rs1_value_out),
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.rs2_value_out(rs2_value_out)
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);
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always_ff @(posedge clk) begin
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pc_out <= pc_in;
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valid_out <= 0;
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alu_op_out <= 4'bx;
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alu_sub_sra_out <= 1'bx;
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alu_src1_out <= 1'bx;
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alu_src2_out <= 1'bx;
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mem_read_en_out <= 0;
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mem_write_en_out <= 0;
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imm_out <= 32'bx;
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casez ({opcode, funct3, funct7})
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{RV32_OPCODE_LUI, RV32_FUNCT3_ANY, RV32_FUNCT7_ANY}: begin
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/* LUI */
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valid_out <= 1;
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alu_op_out <= RV32_ALU_OP_SRC2;
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alu_src2_out <= RV32_ALU_SRC2_IMM;
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imm_out <= imm_u;
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end
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{RV32_OPCODE_AUIPC, RV32_FUNCT3_ANY, RV32_FUNCT7_ANY}: begin
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/* AUIPC */
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valid_out <= 1;
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alu_op_out <= RV32_ALU_OP_ADD_SUB;
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alu_sub_sra_out <= 0;
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alu_src1_out <= RV32_ALU_SRC1_PC;
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alu_src2_out <= RV32_ALU_SRC2_IMM;
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imm_out <= imm_u;
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end
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{RV32_OPCODE_JAL, RV32_FUNCT3_ANY, RV32_FUNCT7_ANY}: begin
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/* JAL */
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valid_out <= 1;
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alu_op_out <= RV32_ALU_OP_SRC1P4;
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alu_src1_out <= RV32_ALU_SRC1_PC;
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imm_out <= imm_j;
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end
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{RV32_OPCODE_JALR, RV32_FUNCT3_ZERO, RV32_FUNCT7_ANY}: begin
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/* JALR */
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valid_out <= 1;
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alu_op_out <= RV32_ALU_OP_SRC1P4;
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alu_src1_out <= RV32_ALU_SRC1_PC;
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imm_out <= imm_i;
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end
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{RV32_OPCODE_BRANCH, RV32_FUNCT3_BRANCH_BEQ, RV32_FUNCT7_ANY}: begin
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/* BEQ */
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valid_out <= 1;
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alu_op_out <= RV32_ALU_OP_ADD_SUB;
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alu_sub_sra_out <= 1;
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alu_src1_out <= RV32_ALU_SRC1_REG;
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alu_src2_out <= RV32_ALU_SRC2_REG;
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imm_out <= imm_b;
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end
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{RV32_OPCODE_BRANCH, RV32_FUNCT3_BRANCH_BNE, RV32_FUNCT7_ANY}: begin
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/* BNE */
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valid_out <= 1;
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alu_op_out <= RV32_ALU_OP_ADD_SUB;
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alu_sub_sra_out <= 1;
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alu_src1_out <= RV32_ALU_SRC1_REG;
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alu_src2_out <= RV32_ALU_SRC2_REG;
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imm_out <= imm_b;
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end
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{RV32_OPCODE_BRANCH, RV32_FUNCT3_BRANCH_BLT, RV32_FUNCT7_ANY}: begin
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/* BLT */
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valid_out <= 1;
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alu_op_out <= RV32_ALU_OP_SLT;
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alu_sub_sra_out <= 1;
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alu_src1_out <= RV32_ALU_SRC1_REG;
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alu_src2_out <= RV32_ALU_SRC2_REG;
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imm_out <= imm_b;
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end
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{RV32_OPCODE_BRANCH, RV32_FUNCT3_BRANCH_BGE, RV32_FUNCT7_ANY}: begin
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/* BGE */
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valid_out <= 1;
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alu_op_out <= RV32_ALU_OP_SLT;
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alu_sub_sra_out <= 1;
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alu_src1_out <= RV32_ALU_SRC1_REG;
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alu_src2_out <= RV32_ALU_SRC2_REG;
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imm_out <= imm_b;
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end
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{RV32_OPCODE_BRANCH, RV32_FUNCT3_BRANCH_BLTU, RV32_FUNCT7_ANY}: begin
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/* BLTU */
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valid_out <= 1;
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alu_op_out <= RV32_ALU_OP_SLTU;
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alu_sub_sra_out <= 1;
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alu_src1_out <= RV32_ALU_SRC1_REG;
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alu_src2_out <= RV32_ALU_SRC2_REG;
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imm_out <= imm_b;
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end
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{RV32_OPCODE_BRANCH, RV32_FUNCT3_BRANCH_BGEU, RV32_FUNCT7_ANY}: begin
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/* BGEU */
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valid_out <= 1;
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alu_op_out <= RV32_ALU_OP_SLTU;
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alu_sub_sra_out <= 1;
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alu_src1_out <= RV32_ALU_SRC1_REG;
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alu_src2_out <= RV32_ALU_SRC2_REG;
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imm_out <= imm_b;
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end
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{RV32_OPCODE_LOAD, RV32_FUNCT3_LOAD_LB, RV32_FUNCT7_ANY}: begin
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/* LB */
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valid_out <= 1;
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alu_op_out <= RV32_ALU_OP_ADD_SUB;
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alu_sub_sra_out <= 0;
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alu_src1_out <= RV32_ALU_SRC1_REG;
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alu_src2_out <= RV32_ALU_SRC2_IMM;
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mem_read_en_out <= 1;
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imm_out <= imm_i;
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end
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{RV32_OPCODE_LOAD, RV32_FUNCT3_LOAD_LH, RV32_FUNCT7_ANY}: begin
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/* LH */
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valid_out <= 1;
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alu_op_out <= RV32_ALU_OP_ADD_SUB;
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alu_sub_sra_out <= 0;
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alu_src1_out <= RV32_ALU_SRC1_REG;
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alu_src2_out <= RV32_ALU_SRC2_IMM;
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mem_read_en_out <= 1;
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imm_out <= imm_i;
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end
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{RV32_OPCODE_LOAD, RV32_FUNCT3_LOAD_LW, RV32_FUNCT7_ANY}: begin
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/* LW */
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valid_out <= 1;
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alu_op_out <= RV32_ALU_OP_ADD_SUB;
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alu_sub_sra_out <= 0;
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alu_src1_out <= RV32_ALU_SRC1_REG;
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alu_src2_out <= RV32_ALU_SRC2_IMM;
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mem_read_en_out <= 1;
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imm_out <= imm_i;
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end
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{RV32_OPCODE_LOAD, RV32_FUNCT3_LOAD_LBU, RV32_FUNCT7_ANY}: begin
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/* LBU */
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valid_out <= 1;
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alu_op_out <= RV32_ALU_OP_ADD_SUB;
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alu_sub_sra_out <= 0;
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alu_src1_out <= RV32_ALU_SRC1_REG;
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alu_src2_out <= RV32_ALU_SRC2_IMM;
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mem_read_en_out <= 1;
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imm_out <= imm_i;
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end
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{RV32_OPCODE_LOAD, RV32_FUNCT3_LOAD_LHU, RV32_FUNCT7_ANY}: begin
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/* LHU */
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valid_out <= 1;
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alu_op_out <= RV32_ALU_OP_ADD_SUB;
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alu_sub_sra_out <= 0;
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alu_src1_out <= RV32_ALU_SRC1_REG;
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alu_src2_out <= RV32_ALU_SRC2_IMM;
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mem_read_en_out <= 1;
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imm_out <= imm_i;
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end
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{RV32_OPCODE_STORE, RV32_FUNCT3_STORE_SB, RV32_FUNCT7_ANY}: begin
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/* SB */
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valid_out <= 1;
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alu_op_out <= RV32_ALU_OP_ADD_SUB;
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alu_sub_sra_out <= 0;
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alu_src1_out <= RV32_ALU_SRC1_REG;
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alu_src2_out <= RV32_ALU_SRC2_IMM;
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mem_write_en_out <= 1;
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imm_out <= imm_s;
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end
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{RV32_OPCODE_STORE, RV32_FUNCT3_STORE_SH, RV32_FUNCT7_ANY}: begin
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/* SH */
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valid_out <= 1;
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alu_op_out <= RV32_ALU_OP_ADD_SUB;
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alu_sub_sra_out <= 0;
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alu_src1_out <= RV32_ALU_SRC1_REG;
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alu_src2_out <= RV32_ALU_SRC2_IMM;
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mem_write_en_out <= 1;
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imm_out <= imm_s;
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end
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{RV32_OPCODE_STORE, RV32_FUNCT3_STORE_SW, RV32_FUNCT7_ANY}: begin
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/* SW */
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valid_out <= 1;
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alu_op_out <= RV32_ALU_OP_ADD_SUB;
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alu_sub_sra_out <= 0;
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alu_src1_out <= RV32_ALU_SRC1_REG;
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alu_src2_out <= RV32_ALU_SRC2_IMM;
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mem_write_en_out <= 1;
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imm_out <= imm_s;
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end
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{RV32_OPCODE_OP_IMM, RV32_FUNCT3_OP_ADD_SUB, RV32_FUNCT7_ANY}: begin
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/* ADDI */
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valid_out <= 1;
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alu_op_out <= RV32_ALU_OP_ADD_SUB;
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alu_sub_sra_out <= 0;
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alu_src1_out <= RV32_ALU_SRC1_REG;
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alu_src2_out <= RV32_ALU_SRC2_IMM;
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imm_out <= imm_i;
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end
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{RV32_OPCODE_OP_IMM, RV32_FUNCT3_OP_SLT, RV32_FUNCT7_ANY}: begin
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/* SLTI */
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valid_out <= 1;
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alu_op_out <= RV32_ALU_OP_SLT;
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alu_sub_sra_out <= 1;
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alu_src1_out <= RV32_ALU_SRC1_REG;
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alu_src2_out <= RV32_ALU_SRC2_IMM;
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imm_out <= imm_i;
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end
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{RV32_OPCODE_OP_IMM, RV32_FUNCT3_OP_SLTU, RV32_FUNCT7_ANY}: begin
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/* SLTIU */
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valid_out <= 1;
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alu_op_out <= RV32_ALU_OP_SLTU;
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alu_sub_sra_out <= 1;
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alu_src1_out <= RV32_ALU_SRC1_REG;
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alu_src2_out <= RV32_ALU_SRC2_IMM;
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imm_out <= imm_i;
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end
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{RV32_OPCODE_OP_IMM, RV32_FUNCT3_OP_XOR, RV32_FUNCT7_ANY}: begin
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/* XORI */
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valid_out <= 1;
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alu_op_out <= RV32_ALU_OP_XOR;
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alu_src1_out <= RV32_ALU_SRC1_REG;
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alu_src2_out <= RV32_ALU_SRC2_IMM;
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imm_out <= imm_i;
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end
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{RV32_OPCODE_OP_IMM, RV32_FUNCT3_OP_OR, RV32_FUNCT7_ANY}: begin
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/* ORI */
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valid_out <= 1;
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alu_op_out <= RV32_ALU_OP_OR;
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alu_src1_out <= RV32_ALU_SRC1_REG;
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alu_src2_out <= RV32_ALU_SRC2_IMM;
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imm_out <= imm_i;
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end
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{RV32_OPCODE_OP_IMM, RV32_FUNCT3_OP_AND, RV32_FUNCT7_ANY}: begin
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/* ANDI */
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valid_out <= 1;
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alu_op_out <= RV32_ALU_OP_AND;
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alu_src1_out <= RV32_ALU_SRC1_REG;
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alu_src2_out <= RV32_ALU_SRC2_IMM;
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imm_out <= imm_i;
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end
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{RV32_OPCODE_OP_IMM, RV32_FUNCT3_OP_SLL, RV32_FUNCT7_ZERO}: begin
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/* SLLI */
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valid_out <= 1;
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alu_op_out <= RV32_ALU_OP_SLL;
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alu_src1_out <= RV32_ALU_SRC1_REG;
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alu_src2_out <= RV32_ALU_SRC2_IMM;
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imm_out <= shamt;
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end
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{RV32_OPCODE_OP_IMM, RV32_FUNCT3_OP_SRL_SRA, RV32_FUNCT7_ZERO}: begin
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/* SRLI */
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valid_out <= 1;
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alu_op_out <= RV32_ALU_OP_SRL_SRA;
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alu_sub_sra_out <= 0;
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alu_src1_out <= RV32_ALU_SRC1_REG;
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alu_src2_out <= RV32_ALU_SRC2_IMM;
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imm_out <= shamt;
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end
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{RV32_OPCODE_OP_IMM, RV32_FUNCT3_OP_SRL_SRA, RV32_FUNCT7_OP_SRA}: begin
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/* SRAI */
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valid_out <= 1;
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alu_op_out <= RV32_ALU_OP_SRL_SRA;
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alu_sub_sra_out <= 1;
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alu_src1_out <= RV32_ALU_SRC1_REG;
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alu_src2_out <= RV32_ALU_SRC2_IMM;
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imm_out <= shamt;
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end
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{RV32_OPCODE_OP, RV32_FUNCT3_OP_ADD_SUB, RV32_FUNCT7_ZERO}: begin
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/* ADD */
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valid_out <= 1;
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alu_op_out <= RV32_ALU_OP_ADD_SUB;
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alu_sub_sra_out <= 0;
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alu_src1_out <= RV32_ALU_SRC1_REG;
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alu_src2_out <= RV32_ALU_SRC2_REG;
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end
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{RV32_OPCODE_OP, RV32_FUNCT3_OP_ADD_SUB, RV32_FUNCT7_OP_SUB}: begin
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/* SUB */
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valid_out <= 1;
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alu_op_out <= RV32_ALU_OP_ADD_SUB;
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alu_sub_sra_out <= 1;
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alu_src1_out <= RV32_ALU_SRC1_REG;
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alu_src2_out <= RV32_ALU_SRC2_REG;
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end
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{RV32_OPCODE_OP, RV32_FUNCT3_OP_SLL, RV32_FUNCT7_ZERO}: begin
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/* SLL */
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valid_out <= 1;
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alu_op_out <= RV32_ALU_OP_SLL;
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alu_src1_out <= RV32_ALU_SRC1_REG;
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alu_src2_out <= RV32_ALU_SRC2_REG;
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end
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{RV32_OPCODE_OP, RV32_FUNCT3_OP_SLT, RV32_FUNCT7_ZERO}: begin
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/* SLT */
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valid_out <= 1;
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alu_op_out <= RV32_ALU_OP_SLT;
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alu_sub_sra_out <= 1;
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alu_src1_out <= RV32_ALU_SRC1_REG;
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alu_src2_out <= RV32_ALU_SRC2_REG;
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end
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{RV32_OPCODE_OP, RV32_FUNCT3_OP_SLTU, RV32_FUNCT7_ZERO}: begin
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/* SLTU */
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valid_out <= 1;
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alu_op_out <= RV32_ALU_OP_SLTU;
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alu_sub_sra_out <= 1;
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alu_src1_out <= RV32_ALU_SRC1_REG;
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alu_src2_out <= RV32_ALU_SRC2_REG;
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end
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{RV32_OPCODE_OP, RV32_FUNCT3_OP_XOR, RV32_FUNCT7_ZERO}: begin
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/* XOR */
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valid_out <= 1;
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alu_op_out <= RV32_ALU_OP_XOR;
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alu_src1_out <= RV32_ALU_SRC1_REG;
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alu_src2_out <= RV32_ALU_SRC2_REG;
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end
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{RV32_OPCODE_OP, RV32_FUNCT3_OP_SRL_SRA, RV32_FUNCT7_ZERO}: begin
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/* SRL */
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valid_out <= 1;
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alu_op_out <= RV32_ALU_OP_SRL_SRA;
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alu_sub_sra_out <= 0;
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alu_src1_out <= RV32_ALU_SRC1_REG;
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alu_src2_out <= RV32_ALU_SRC2_REG;
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end
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{RV32_OPCODE_OP, RV32_FUNCT3_OP_SRL_SRA, RV32_FUNCT7_OP_SRA}: begin
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/* SRA */
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valid_out <= 1;
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alu_op_out <= RV32_ALU_OP_SRL_SRA;
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alu_sub_sra_out <= 1;
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alu_src1_out <= RV32_ALU_SRC1_REG;
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alu_src2_out <= RV32_ALU_SRC2_REG;
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end
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{RV32_OPCODE_OP, RV32_FUNCT3_OP_OR, RV32_FUNCT7_ZERO}: begin
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/* OR */
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valid_out <= 1;
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alu_op_out <= RV32_ALU_OP_OR;
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alu_src1_out <= RV32_ALU_SRC1_REG;
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alu_src2_out <= RV32_ALU_SRC2_REG;
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end
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{RV32_OPCODE_OP, RV32_FUNCT3_OP_AND, RV32_FUNCT7_ZERO}: begin
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/* AND */
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valid_out <= 1;
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alu_op_out <= RV32_ALU_OP_AND;
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alu_src1_out <= RV32_ALU_SRC1_REG;
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alu_src2_out <= RV32_ALU_SRC2_REG;
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end
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endcase
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end
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endmodule
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`endif
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